An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

Tobajas, F.; Callicó, Gustavo M.; Pérez, Patrick; Armas, V. de; Sarmiento, Roberto

doi:10.1109/tce.2008.4470035

Cited by 33 publications

(12 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The design by [19] requires almost the same area as ours, however, we provide 63% higher throughput. While on the other hand, reference [14] provides almost the same throughput as we do, we require 35% less area in terms of equivalent gates.…”

Section: Resultsmentioning

confidence: 74%

“…The comparisons with [19] and [14] need some clarification. The design by [19] requires almost the same area as ours, however, we provide 63% higher throughput.…”

Section: Resultsmentioning

confidence: 99%

“…These solutions provide higher throughput at the cost of additional on-chip area requirement, but still most of these solutions do not meet the throughput requirements of all the levels (level 1-5.1) offered by the Video Codec H.264/AVC. For instance, F. Tobajas [19] proposed a hardware architecture based on a double-filter strategy, and use a raster scan filtering order. Cheng [14], [17] proposes a configurable window-based architecture to simultaneously filter in both the directions.…”

Section: Related Workmentioning

confidence: 99%

“…RAM units are shared between the transpose and BS units to serve as temporary storage location. The cost of a register file consisting of 14 32-bit registers [19] is about 3.3k gates whereas the multiplexers depicted in Figure 10 cost only 500 gates (implemented on 0.18 μm CMOS standard cell technology). This optimization delivers area saving.…”

Section: Architecture Level Optimizationmentioning

confidence: 99%

See 3 more Smart Citations

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Nadeem

Wong

Kuzmanov

et al. 2009

2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia

View full text Add to dashboard Cite

In this paper, we present a high-throughput, areaefficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard. In order to achieve this goal, we start with algorithmic optimization and propose a novel decomposition of the filter kernels for the deblocking filter. The proposed decomposition reduces the number of adders by 51% and thereby greatly reduces the area requirement for its implementation. Subsequently, at architecture level, while using two identical filtering units, the transpose units are realized by efficient reuse of hardware resources to further reduce the area requirement. The two filtering units process the horizontal and vertical edges of the macro-block simultaneously and therefore further enhance the throughput of the hardware accelerator. Several other optimization techniques, such as reuse of intermediate results, pipelining, and merging of processing blocks on critical path, result in a hardware accelerator for deblocking filter with high throughput at one hand and less area in terms of equivalent gates count on the other, when compared with existing state-ofthe-art hardware accelerators in the literature. While working at clock frequency of 166 MHz, synthesized under 0.18 μm CMOS standard cell technology, it easily meets the throughput requirements of all the levels in H.264/AVC video coding standard and consumes only 12.06 K gates (excluding SRAM).

show abstract

Section: Resultsmentioning

confidence: 74%

“…The comparisons with [19] and [14] need some clarification. The design by [19] requires almost the same area as ours, however, we provide 63% higher throughput.…”

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Architecture Level Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Nadeem

Wong

Kuzmanov

et al. 2009

2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia

View full text Add to dashboard Cite

show abstract

“…In fact, there exist several DF hardware implementation approaches in the literature. They are mainly focused on reducing cycles on a macroblock filtering process, exploiting different techniques [6][7][8]. However, their common drawbacks are that they have to process MBs sequentially, filtering them one by one, and that almost everyone of them are, static solutions.…”

Section: Introductionmentioning

confidence: 99%

Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation

Cervero

Otero

Torre

et al. 2011

VLSI Circuits and Systems V

View full text Add to dashboard Cite

One of the most computational intensive tasks in recent video encoders and decoders is the deblocking filter. Its computational complexity is considerable, and it might take more than 30% of the total computational cost of the decoder execution. Nowadays, some of its limiting factors for reaching real-time capabilities are mainly related with memory and speed. Trying to deal with these factors, this paper proposes a novel Deblocking filter architecture which supports all filtering modes available in both the H.264/AVC and Scalable Video Coding (SVC) standards. It has been implemented in a hardware scalable architecture, which benefits of the parallelism and adaptability of the algorithm and which can be adapted dynamically in FPGAs.Regarding to the parallelism, this architecture mapping is capable of respecting data dependencies among MBs while several functional units (FU) are filtering data in parallel. Regarding scalability, the architecture is flexible enough for adapting its performance to the diverse environment demands. This fact is possible by increasing or decreasing the number of FUs, like in a systolic array. In this sense, this paper will present a composition between the FU proposed against the state-of-the art work.

show abstract

Adaptive Low-Power Architectures for Embedded Multimedia Systems

Shafique

Henkel

2011

Hardware/Software Architectures for Low-Power Embedded Multimedia Systems

View full text Add to dashboard Cite

An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

Cited by 33 publications

References 14 publications

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation

Adaptive Low-Power Architectures for Embedded Multimedia Systems

Contact Info

Product

Resources

About