A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Abstract

In this paper, we present a high-throughput, areaefficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard. In order to achieve this goal, we start with algorithmic optimization and propose a novel decomposition of the filter kernels for the deblocking filter. The proposed decomposition reduces the number of adders by 51% and thereby greatly reduces the area requirement for its implementation. Subsequently, at architecture level, while using two identical filtering units, the transpose units are realized by efficient reuse of hardware resources to further reduce the area requirement. The two filtering units process the horizontal and vertical edges of the macro-block simultaneously and therefore further enhance the throughput of the hardware accelerator. Several other optimization techniques, such as reuse of intermediate results, pipelining, and merging of processing blocks on critical path, result in a hardware accelerator for deblocking filter with high throughput at one hand and less area in terms of equivalent gates count on the other, when compared with existing state-ofthe-art hardware accelerators in the literature. While working at clock frequency of 166 MHz, synthesized under 0.18 μm CMOS standard cell technology, it easily meets the throughput requirements of all the levels in H.264/AVC video coding standard and consumes only 12.06 K gates (excluding SRAM).

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

“…There exist numerous applications for accelarators in both of the embedded and high performance computing markets. Examples include video processing [24], software-defined radio [5], network traffic management [19], DNA computing [17] and fully programmable hardware acceleration platforms [23]. Efficient sharing of data in a heterogeneous MpSoC which contains different types of integrated computational elements is a challenging task.…”

Low-power, high-throughput deblocking filter for H.264/AVC

“…We proposed a novel decomposition of the filter kernels to remove the arithmetic operations redundancy in our previous work [17]. The proposed optimization of the filter equations reduces the total number of adder instances from 49 to 24 [17]. This more than double reduction of addition operations does not only pay off in terms of less area requirement for its implementation but also helps to reduce the signal activity in the combinatorial logic between different pipeline stages.…”

“…(14) - (16) in Fig 3(c). Similarly, the overlapped data path for conditional filtering in strong and weak filtering modes is implemented in LumaCommonPBlock and LumaCommonQBlock whereas the LumaBs4_PBlock, LumaBs4_QBlock implements the rest of the processing for strong filter mode case [17]. In case of Strong or Weak Filter Modes for chroma component of the MB, one can see from Fig.…”

“…In the original filter equations in H.264/AVC video coding standard [1], 49 addition operations along with 5 clip operations are required in total for full pipeline implementation of the algorithm. We proposed a novel decomposition of the filter kernels to remove the arithmetic operations redundancy in our previous work [17]. The proposed optimization of the filter equations reduces the total number of adder instances from 49 to 24 [17].…”

A high-throughput low-power hardware architecture for H.264 deblocking filter

“…A large number of accelerators utilize a single filter core, such as [4][5][6][7][8][9][10][11][12][13][14]. Most single filter based architecture [4][5][6] can operate at 100MHz and take around 200 cycles per macroblock, which can not satisfy high level requirement.…”