Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

Sadri, Mohammadsadegh; Weis, Christian; Wehn, Norbert; Benini, Luca

doi:10.1145/2513683.2513688

Cited by 63 publications

(21 citation statements)

References 16 publications

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“…DTE IPs have been shown to have limited memory access in previous works. For example, the maximum performance of these engines reported in [13] at 100 MHz is around 400 MB/s and at a frequency of 125 MHz is less than 500 MB/s [19]. Based on Eq.…”

Section: Proposed Memory Architecturementioning

confidence: 99%

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Ayat¹,

Khalil-Hani²,

Rahman³

2018

Turk J Elec Eng & Comp Sci

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Abstract:In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

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Section: Proposed Memory Architecturementioning

confidence: 99%

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Ayat¹,

Khalil-Hani²,

Rahman³

2018

Turk J Elec Eng & Comp Sci

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“…First results are given by Sadri et al [5]. They analyzed the memory interfaces of the Zynq-7020 with a focus on the Accelerator Coherency Port (ACP), which allows coherent access from IP cores implemented in logic to main memory.…”

Section: Related Workmentioning

confidence: 99%

“…It also does not give an overview of the available memory bandwidth for different access patterns. Similar to [5], it does not cover the combination of multiple ports to increase the overall memory bandwidth.…”

Section: Related Workmentioning

confidence: 99%

A Quantitative Analysis of the Memory Architecture of FPGA-SoCs

Göbel

Elhossini

Ching³

et al. 2017

Lecture Notes in Computer Science

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Abstract. In recent years, so called FPGA-SoCs have been introduced by Intel (formerly Altera) and Xilinx. These devices combine multi-core processors with programmable logic. This paper analyzes the various memory and communication interconnects found in actual devices, particularly the Zynq-7020 and Zynq-7045 from Xilinx and the Cyclone V SE SoC from Intel. Issues such as different access patterns, cache coherence and full-duplex communication are analyzed, for both generic accesses as well as for a real workload from the field of video coding. Furthermore, the paper shows that by carefully choosing the memory interconnect networks as well as the software interface, high-speed memory access can be achieved for various scenarios.

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“…The authors thank Mohammadsadegh Sadri from University of Bologna for providing his implementation of AXI master on ACP [18].…”

Section: Acknowledgmentsmentioning

confidence: 99%

THOR - The hardware onion router

Güneysu

Regazzoni²,

Sasdrich

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Security and privacy of data traversing internet have always been a major concern for all users. In this context, The Onion Routing (Tor) is the most successful protocol to anonymize global Internet traffic and is widely deployed as software on many personal computers or servers. In this paper, we explore the potential of modern reconfigurable devices to efficiently realize the Tor protocol on embedded devices. In particular, this targets the acceleration of the complex cryptographic operations involved in the handshake of routing nodes and the data stream encryption. Our hardware-based implementation on the Xilinx Zynq platform outperforms previous embedded solutions by more than a factor of 9 with respect to the cryptographic handshake -ultimately enabling quite inexpensive but highly efficient routers. Hence, we consider our work as a further milestone towards the development and the dissemination of low-cost and high performance onion relays that hopefully ultimately leads again to a more private Internet.

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Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

Cited by 63 publications

References 16 publications

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

A Quantitative Analysis of the Memory Architecture of FPGA-SoCs

THOR - The hardware onion router

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