This paper proposes an efficient particle swarm optimization (PSO) technique that can handle multi-objective optimization problems. It is based on the strength Pareto approach originally used in evolutionary algorithms (EA). The proposed modified particle swarm algorithm is used to build three hybrid EA-PSO algorithms to solve different multi-objective optimization problems. This algorithm and its hybrid forms are tested using seven benchmarks from the literature and the results are compared to the strength Pareto evolutionary algorithm (SPEA2) and a competitive multi-objective PSO using several metrics. The proposed algorithm shows a slower convergence, compared to the other algorithms, but requires less CPU time. Combining PSO and evolutionary algorithms leads to superior hybrid algorithms that outperform SPEA2, the competitive multi-objective PSO (MO-PSO), and the proposed strength Pareto PSO based on different metrics.

Hough transform (HT) is a widely used algorithm in machine vision systems. In this paper, a memory efficient architecture for implementing HT on FPGAs is presented. The proposed architecture enables storing the HT space on the FPGA's memory blocks with no need for accessing external memory while processing large size images in real-time with high frame rate. It can be used for both line and circle detection. Results show very good accuracy with images processed at 30 fps frame rate and image size of 800 × 600. This compares favourably with other reported architectures in the literature. Index Terms-Hough Transform, FPGA, Computer vision 1. INTRODUCTIONIn the past decade, the use of reconfigurable hardware, and particularly FPGAs, has increased dramatically in the field of image processing and machine vision systems Hough Transform (HT) is commonly used for detecting straight lines in images [1]. Implementing this algorithm on FPGAs is challenging due to the high demand on memory storage and the complexity of the algorithm. Normally external memory is used to store the HT data [2,3,4]. This introduces limitations on the bandwidth of the data transfer which leads to limiting the size of the image window and frame rate. This is particularly the case when HT is extended to detect circles and other shapes [4,5,6]. In this paper we present an architecture to implement the HT for both straight lines and circles. It employs an efficient memory design that eliminates the need to use external memory and allows processing of large image sizes at a high frame rate. This paper is organized as follows: Section 2 covers background material about the HT while Section 3 surveys related work. Section 4 introduces the proposed architecture and FPGA implementation. Section 5 presents testing, results, and discussion. Finally section 6 concludes the paper. BACKGROUNDHT works on the contour points resulting from the edge detection process. Each contour point contributes in a voting process for several instances of the object being detected. For each instance a memory location is used to store its vote. The memory used to store the votes of all instances of the object is called HT space. The local minima in the HT space represents the object that received the maximum number of votes. A parameterized model of the object should be provided to relate contour pixels position to the object template. Straight line equation can be expressed in a parameterized form asThe HT space constructed using Equation 1 is a two dimensional space where each point in the space represents a line that corresponds to a single value of and . Each new pixel is used to compute the value of using the position of the pixel (x, y) for each angle . The vote for the line defined by and is then incremented. The HT space should be sampled to allow a limited memory size to store the voting results. Sampling the HT space affects the accuracy of the resulting transform, but is essential for efficient hardware implementation. HT can be modified to detect other shapes by mo...

Abstract-In the era of multicore systems, it is expected that the number of cores that can be integrated on a single chip will be 3-digit. The key to utilize such a huge computational power is to extract the very fine parallelism in the user program. This is nontrivial for the average programmer, and becomes very hard as the number of potential parallel instances increases. Task-based programming models such as OmpSs are promising, since they handle the detection of dependencies and synchronization for the programmer. However, state-of-the-art research shows that task management is not cheap, and introduces a significant overhead that limits the scalability of OmpSs. Nexus# is a hardware accelerator for the OmpSs runtime system, which dynamically monitors dependencies between tasks. It is fully synthesizable in VHDL, and has a distributed task graph model to achieve the best scalability. Supporting tasks with arbitrary number of parameters and any dependency pattern, Nexus# achieves better performance than Nanos, the official OmpSs runtime system, and scales well for the H264dec benchmark with very fine grained tasks, among other benchmarks from the Starbench suite.

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Abstract-Task-based parallel programming models with explicit data dependencies, such as OmpSs, are gaining popularity, due to the ease of describing parallel algorithms with complex and irregular dependency patterns. These advantages, however, come at a steep cost of runtime overhead incurred by dynamic dependency resolution. Hardware support for task management has been proposed in previous work as a possible solution. We present VSs, a runtime library for the OmpSs programming model that integrates the Nexus++ hardware task manager, and evaluate the performance of the VSs-Nexus++ system. Experimental results show that applications with fine-grain tasks can achieve speedups of up to 3.4×, while applications optimized for current runtimes attain 1.3×. Providing support for hardware task managers in runtime libraries is therefore a viable approach to improve the performance of OmpSs applications.

Abstract-GPUs are much more power-efficient devices compared to CPUs, but due to several performance bottlenecks, the performance per watt of GPUs is often much lower than what could be achieved theoretically. To sustain and continue high performance computing growth, new architectural and application techniques are required to create power-efficient computing systems. To find such techniques, however, it is necessary to study the power consumption at a detailed level and understand the bottlenecks which cause low performance. Therefore, in this paper, we study GPU power consumption at component level and investigate the bottlenecks that cause low performance and low energy efficiency. We divide the low performance kernels into low occupancy and full occupancy categories. For the low occupancy category, we study if increasing the occupancy helps in increasing performance and energy efficiency. For the full occupancy category, we investigate if these kernels are limited by memory bandwidth, coalescing efficiency, or SIMD utilization.

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