A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

Sarmiento, Roberto; Tobajas, F.; Armas, V. de; Esper-Chain, R.; Lopez, J.F.; Montiel–Nelson, Juan A.; Núñez, Antonio

doi:10.1109/92.661241

Cited by 17 publications

(6 citation statements)

References 16 publications

(27 reference statements)

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“…The basic concept of CORDIC is to decompose the desired rotation angles into several easy-to-be-implemented subangles [12,13,14]. The subangles can be implemented by the shift-and-add.…”

Section: Processing Element (Pe) Designmentioning

confidence: 99%

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Kuo

Wen

Lin

et al. 2003

EURASIP J. Adv. Signal Process.

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The technique of {orthogonal frequency division multiplexing (OFDM)} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT)} and {inverse FFT (IFFT)} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE)} based on the {{coordinate} rotation digital computer (CORDIC)} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35Ã¢Â€Â‰ÃŽÂ¼m 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048)-point FFT/IFFT operations up to 80Ã¢Â€Â‰MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256Ã¢ÂˆÂ¼2K), DAB, and 2K-mode DVB

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“…The basic concept of CORDIC is to decompose the desired rotation angles into several easy-to-be-implemented subangles [12,13,14]. The subangles can be implemented by the shift-and-add.…”

Section: Processing Element (Pe) Designmentioning

confidence: 99%

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Kuo

Wen

Lin

et al. 2003

EURASIP J. Adv. Signal Process.

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“…In this sub-Section, we evaluate and compare the performance and complexity of a CORDIC and a complex multiplier in phase rotation. In Table 3, the conventional CORDIC algorithm refers to the radix-2 CORDIC, and radix-2=4 CORDIC refers to the work in [14] that enhances operation speed and reduces 25% of the micro-rotation stages. The complex multiplier used in the proposed chip consists of three multiplications and five additions [15].…”

Section: Complex Multiplier Against Cordicmentioning

confidence: 99%

“…To make a fair comparison, we set the precision to 16 bits in all algorithms. To avoid rounding error propagation [14,16], 19 bits are allocated in the data path of the CORDIC-based architectures.…”

Section: Complex Multiplier Against Cordicmentioning

confidence: 99%

“…In [14], the ROM table is further reduced to N=8 words with 23 bits per word due to the higher radix adopted in the later stages. According to the authors, each stage is based on a similar cell with a 4-2 adder=subtracter using two-level carry-save adders (CSA) and redundant arithmetic representation intended to improve the performance.…”

Section: Complex Multiplier Against Cordicmentioning

confidence: 99%

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Low-power variable-length fast Fourier transform processor

Lin

Tsai

Chiueh

2005

IEE Proc., Comput. Digit. Tech.

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Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path delay feedback architecture. The processor can be used in various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber loop (ADSL) and very-high-speed digital subscriber loop (VDSL). To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In addition, techniques including complex multipliers containing three real multiplications, and reduced sine/cosine tables are adopted. The chip is fabricated using a 0.35 mm CMOS process and it measures 3900 mm £ 5500 mm. According to the measured results, the 2048-point FFT operation can function correctly up to 45 MHz with a 3.3 V supply voltage and power consumption of 640 mW. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176 mW when it runs at 17.8 MHz.

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“…In this paper, the DIT Radix-4 algorithm is derived and its efficient butterfly structure is proposed for SoC(System on a Chip) implementation. 방법이 제안되었다 [1][2][3][4] . 이와 비교하여 DIT는 순차적 인 출력을 낼 수 있는 장점이 있음에도 다양한 알고리 즘이 개발되지 못하였다 [5] .…”

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