The technique of {orthogonal frequency division multiplexing (OFDM)} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT)} and {inverse FFT (IFFT)} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE)} based on the {{coordinate} rotation digital computer (CORDIC)} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048)-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K), DAB, and 2K-mode DVB
Orfhogonal Frequency Division Mu1fipleri.g (OFDM) system is famous for its robustness against frequency selective fading channel. The Fasf Fourier Transform (FFT) and Inverse FFT (IFFT) processor are used as the modulation/demodulation kernel in the OFDM systems. The sizes of FFTLlFFT .processors are varied in the different applications of OFDM systems. In this paper, we design and implement a programmable 64-2048-point FFTnFFT processor to cover the different specifications of OFDM applications. The cached-memory architecture is our suggested VLSl system architecture. We implement the Processing Element (PE) by using CORDIC algorithm to replace the multiplier-based PE. We also proposed d4prerofafion and modified EEAS-CORDIC VLSI architecture to reduce the iteration number and quantization noise. Finally, we implement the FFT processor with TSMC 0.35 p m 1P4M CMOS technology. The die area of the FFT/IFFT processor is 12.25 mm' including.2048~32 bits memory. The inputloutput wordlength is 16-bit wide. The chip can operate under 80 MHz and meet most standard requirements (64-2048 points).
This paper describes a new design approach and an architecture for a Direct Digital Frequency Synthesizer (DDFS) based on Least Square (LS) approximation. It is shown that the architecture can be implemented as a lowcost, low-power, feedforward, and easily pipelineable datapath. A prototype IC has been designed and fabricated in TSMC 0.25 um CMOS technology. The IC produces 14-bit sine and cosine outputs with a spurious free dynamic range of 100 dBc. A 32-bit frequency word gives a tuning resolution of 0.0466 Hz at 200 MHz sampling rate.
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