Low-power variable-length fast Fourier transform processor

Abstract

Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path delay feedback architecture. The processor can be used in various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber loop (ADSL) and very-high-speed digital subscriber loop (VDSL). To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In addition, techniques including complex multipliers containing three real multiplications, and reduced sine/cosine tables are adopted. The chip is fabricated using a 0.35 mm CMOS process and it measures 3900 mm £ 5500 mm. According to the measured results, the 2048-point FFT operation can function correctly up to 45 MHz with a 3.3 V supply voltage and power consumption of 640 mW. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176 mW when it runs at 17.8 MHz.

A Block Scaling FFT/IFFT Processor for WiMAX Applications

“…We can find that the FFT processor [9] use a shorter wordlength of 12 bits since it only supports for 9-bit input. The processor [8] has employed the BFP approach and thus the wordlength is not increased.…”

“…For comparisons, we choose two FFT processor chips which can handle consecutive 2048-point FFT computations [8], [9]. Since these two chips can not support multiple data streams and only complete results for 1024-point FFT are listed, the comparisons of execution time and power are based on single-stream 1024-point FFT.…”

“…The processor [8] has employed the BFP approach and thus the wordlength is not increased. However, both designs [8], [9] do not employ a cache design to reduce the power of memory accesses. From this comparison, it is shown that our proposal has a satisfactory result in both normalized area and FFTs per energy, which justifies the feasibility of the proposed method.…”

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

“…The custom scalable IP core Zhao [6], employs single memory architecture with clock gating. The custom variable-length Lin [7] FFT-processor employs radix-2/4/8 single-path delay algorithm. MIT FFT uses subtreshold circuit techniques [8].…”

Programmable N-Point FFT Design

“…The area of variable length FFT Processors has been largely unexplored. A variable-length FFT processor that integrates two radix-2 stages and three radix-2 3 stages for FFT sizes 512, 1024 and 2048 was proposed in [10]. Ref.…”