A Block Scaling FFT/IFFT Processor for WiMAX Applications

Chen, Yuan; Lin, Yu‐Wei; Lee, Chen‐Yi

doi:10.1109/asscc.2006.357886

Cited by 25 publications

(12 citation statements)

References 7 publications

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“…In order to reduce the hardware costs due to the four-path multiplication in our design, only two complex multipliers [10] are employed for the scheduled twiddle-factor multiplication between adjacent iteration. Compared to the usage of seven complex multipliers based on eight-path radix-8 operations as presented in [8] and [9], the resource reduction is significant while the high throughput requirement is preserved. In addition, a hardware-efficient constant multiplication scheme [11] is further used to simplify the radix-internal multiplication.…”

Section: A Simplified Multiplication Schemes For the Fft Kernelmentioning

confidence: 97%

“…From Table II, it is observed that relatively lower power consumption can be obtained for our design to achieve the same throughput for OCT/2048-point FFT or WLAN/128-piint FFT modes. Moreover, when performing the WLAN 128-point FFT×4 at a required 160 MS/s throughput rate [4], the power consumption is slightly varied for our chip (in a similar level to OCT 2048-point FFT×2), compared to the significant power increment using the design in [8] and [9]. Thus, the proposed FFT processor is suitable for the dual OCT/WLAN applications with exhibited energy-efficiency improvement.…”

Section: Chip Design and Comparisonmentioning

confidence: 98%

“…OCT/2048-point FFT×2 (T.R.~40×2=80MS/s) 69.2@40 MHz 93.9 *1 @40MHz 104 *2 @40MHz WLAN/128-point FFT×4 (T.R.~40×4=160MS/s) 72.7@40 MHz 140.8 *1 @60MHz 156 *2 @60MHz *1 this value is normalized from power consumption @ 22.86 MHz in [8] *2 this value is normalized from power consumption @ 20 MHz in [9] *3 the T.R. is specified based on radix-2 3 /2 3 /2 operations for [8] and [9] …”

Section: Nor Power Consumption (Mw)mentioning

confidence: 99%

“…3, consisting of two sets of four-bank 4096-word SRAMs and a multimode FFT kernel, where the two sets of memory are accessed alternatively [8], [9] 3], corresponding to selection of memory bank, address and complex data word, respectively, as shown in Fig. 2.…”

Section: Proposed Fft Architecturementioning

confidence: 99%

“…7. In order to improve the signal-to-quantization-noise ratio (SQNR), the block floating point (BFP) scheme [8], [11] is employed to achieve a SQNR of 48 dB using 12-bit wordlegth. By post-layout simulation, the proposed FFT chip can perform OCT/2048-point FFT×2 and WLAN/128-point FFT×4 at 40 MHz with power consumption of 69.2 mW and 72.7 mW, respectively.…”

Section: Chip Design and Comparisonmentioning

confidence: 99%

See 4 more Smart Citations

A dual-application low-power FFT processor for WLAN-integrated SD-OCT systems

Tang

Jan

et al. 2012

The 1st IEEE Global Conference on Consumer Electronics 2012

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This paper presents a dual-application FFT processor for spectral domain optical coherence tomography (SD-OCT) systems integrated with a wireless local area networking (WLAN) module. A high-radix multimode FFT kernel together with the four-path memory-data access scheme is proposed to improve the hardware efficiency. By the proposed memory-based architecture, multimode 2048/1024-point FFT×2 (for SD-OCT) or 128/64-point FFT×4 (for WLAN) can be performed in an energy-efficient manner. A test chip has been designed using a TSMC 0.18μm process with a core area of 4.12 mm 2 . Through post-layout simulation, the power consumption is 69.2 mW and 72.7 mW at 40 MHz for OCT/2048-point FFT×2 and WLAN/128-point FFT×4 modes, respectively. Compared to the referred, the power saving of 26%~53% can be achieved using the proposed design.

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Section: A Simplified Multiplication Schemes For the Fft Kernelmentioning

confidence: 97%

Section: Chip Design and Comparisonmentioning

confidence: 98%

Section: Nor Power Consumption (Mw)mentioning

confidence: 99%

Section: Proposed Fft Architecturementioning

confidence: 99%

Section: Chip Design and Comparisonmentioning

confidence: 99%

See 3 more Smart Citations

A dual-application low-power FFT processor for WLAN-integrated SD-OCT systems

Tang

Jan

et al. 2012

The 1st IEEE Global Conference on Consumer Electronics 2012

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A two-hop equalize-and-forward relay scheme in OFDM-based wireless networks over multipath channels

Gao

Wang

Leung

2015

Wirel. Commun. Mob. Comput.

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Relay communications have attracted increasing research attentions as a cost-effective technique to improve spatial diversity, service coverage, and energy efficiency in wireless networks. However, existing relay schemes (e.g., amplifyand-forward and decode-and-forward (DF) schemes) still face several major challenges, particularly the accumulation of multipath channels effect in AF and long processing latency in DF. To address these issues, we propose a novel equalizeand-forward (EF) relay scheme to enhance the retransmission reliability while maintaining low processing delay at the relay node. In particular, the proposed EF relay estimates and equalizes the channel between source and relay to eliminate the channel accumulation effect without signal regeneration. To further reduce the relay processing time, the channel estimation and equalization in the proposed EF design are performed in parallel. The proposed equalization is realized by presetting the equalizer coefficients with the current channel response that is predicted in parallel using multiple past channel responses. Numerical results show that the proposed EF relay scheme can achieve comparable symbol error rate performance as the DF relay with much less relay latency. In addition, the EF relay exhibits low outage probability at the same data rate as compared with traditional amplify-and-forward and DF schemes.

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A 820 Mb/s baseband processor LSI based on LDPC coded OFDM for UWB systems

Nakamura

Shimizu

et al. 2008

2008 IEEE Asian Solid-State Circuits Conference

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This paper presents a high-throughput and highlyreliable baseband processor LSI based on LDPC coding OFDM UWB. This LSI targets for wireless LAN systems inside a car which enable to translate a high-resolution video under noisy environment. A chip capable of operating at 147MHz was fabricated using UMC 0.13 m 1P8M CMOS technology. By adopting the OFDM modulation with 1024 sub-carriers, it achieves a throughput of 820Mb/s and 10 -4 BER performance under 30dB CNR with 5/6 coding rate. Power dissipation is 189mW/391mW (TX/RX).

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A Block Scaling FFT/IFFT Processor for WiMAX Applications

Cited by 25 publications

References 7 publications

A dual-application low-power FFT processor for WLAN-integrated SD-OCT systems

A dual-application low-power FFT processor for WLAN-integrated SD-OCT systems

A two-hop equalize-and-forward relay scheme in OFDM-based wireless networks over multipath channels

A 820 Mb/s baseband processor LSI based on LDPC coded OFDM for UWB systems

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