On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.
A method is presented to determine a transfer function for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying material, such as a polysilicon gate. The image fading technique was employed to determine the dependence of photoresist LER on the image-log-slope (ILS) of the aerial image. From this initial condition in resist, LER after the etch process was measured in polysilicon and related to the ILS used to pattern the resist. From these two relationships, a transfer function could be derived to quantify the magnitude of LER that transfers into the polysilicon under layer from the photoresist. A gate layer type film stack and a 193nm resist system were employed. Results demonstrated that photoresist LER did transfer through the etch process. Increasing the resist LER increased the post-etch LER in polysilicon, and accordingly, minimizing resist LER minimized polysilicon LER. The etch process can reduce the magnitude of roughness in polysilicon over a range of mid and low spatial frequencies, however the extent of the roughness reduction diminishes as the resist LER reaches its minimum at large values of the ILS. In addition, resist trim rates during etch were apparently increased when LER of the resist was large. These results demonstrate that post-etch LER in polysilicon may be limited by the minimum LER achievable in resist, despite the occurrence of apparent smoothing mechanisms through the etch process.
Microfield exposure tools (METs) continue to play a dominant role in the development of extreme ultraviolet resists. One of these tools is the 0.3 numerical aperture SEMATECH Berkeley MET operating as a resist and mask test center. Here the authors present an update on this tool, summarizing the latest test and characterization results. They provide an update on the long-term aberration stability of the tool and present line-space imaging in chemically amplified photoresist down to the 20nm half-pitch level. Although resist development has shown substantial progress in the area of resolution, line edge roughness (LER) remains a significant concern. In this manuscript the authors further present a summary of recent LER performance results and consider the effect of mask contributors to the LER observed from the SEMATECH Berkeley MET.
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