No abstract

The 2007 International Technology Roadmap for Semiconductors (ITRS) 1 specifies Extreme Ultraviolet (EUV) lithography as one leading technology option for the 32nm half-pitch node, and significant world wide effort is being focused towards this goal. Readiness of EUV photoresists is one of the risk areas. In 2007, the ITRS modified performance targets for high-volume manufacturing EUV resists to better reflect fundamental resist materials challenges. For 32nm half-pitch patterning at EUV, a photospeed range from 5-30 mJ/cm 2 and low-frequency linewidth roughness target of 1.7nm (3σ) have been specified. Towards this goal, the joint INVENT activity (AMD, CNSE, IBM, Micron, and Qimonda) at Albany evaluated a broad range of EUV photoresists using the EUV MET at Lawrence Berkeley National Laboratories (LBNL), and the EUV interferometer at the Paul Scherrer Institut (PSI), Switzerland. Program goals targeted resist performance for 32nm and 22nm groundrule development activities, and included interim relaxation of ITRS resist performance targets. This presentation will give an updated review of the results. Progress is evident in all areas of EUV resist patterning, particularly contact/via and ultrathin resist film performance. We also describe a simplified figure-of-merit approach useful for more quantitative assessment of the strengths and weaknesses of current materials.

A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form an MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.

For the patterning of sub-100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, from a fundamental as well as a manufacturing perspective. With the migration to thin photoresists coupled with bottom antireflective coating (ARC)-hardmask underlayers, LER analysis of the developed resist structures is perhaps an inaccurate representation of the substrate roughness after the etch process, since those underlayers can play a significant role in increasing/decreasing linewidth variations during the image transfer process and hence can impact the device performance. In this article, atomic force microscopy is used to investigate the contribution of the imaging resist sidewall topography to the sidewall roughness of the final etched feature in thin photoresists, ARC, and hardmasks. Resist systems suitable for 248 and 193 nm lithography as well as fluorine-containing resists were processed using N2-H2 or fluorocarbon plasma etch. It is shown that the interaction of different etch chemistries with existing sidewall profiles can result in loss of the original morphological information and creation of new spatial frequency domains that act as physical templates for subsequent image transfer processes. Excessive roughness transfer into the hardmask layer due to insufficient resist thickness or inadequate etch resistance originates from striation propagation from the resist layer into the hardmask layer. In the case of fluorine-containing materials, a decreased etch resistance and reduced initial film thickness values give rise to critical underlayer roughening during plasma etch. Based on the results shown, it is predicted that advanced resist systems for 157 nm lithography and beyond will require the use of ARC layers with built-in hardmask properties in those particular cases in which patterning of deep trenches is needed, in order to maintain LER values within acceptable levels.

We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.