Modeling line edge roughness effects in sub 100 nanometer gate length devices

Abstract

A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form an MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.

Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness

“…Various sources of intrinsic parameter fluctuations have been studied using numerical simulations with a preference given in the past to random discrete dopants in the active region of the transistor [5]- [7], random dopants and grain boundaries in the polysilicon gate [8] and oxide thickness fluctuations [9]. The line edge roughness (LER) caused by tolerances inherent to materials and tools used in the lithography processes is yet another source of intrinsic parameter fluctuations [10], [11] which needs close attention. LER has caused little worry in the past since the critical dimensions of MOSFETs were orders of magnitude larger than the roughness.…”

“…As shown in Fig. 1 the edge roughness remains typically on the order of 5 nm almost independently of the type of lithography used in production or research [10], [12]- [17]. Although attempts have been made to simulate analytically the impact of the gate edge roughness on leakage [18] they rely on fitting parameters and lack predictive power due to the complex three-dimensional (3-D) nature of the problem.…”

“…Pioneering 3-D simulation studies treat the problem deterministically using a "square wave" approximation for the gate edge [19], [20]. The simplified statistical approach adopted in [10], [21], [22] is based on 2-D simulations of samples of MOSFETs with statistical variations in the channel length but fixed channel width. The attempt to validate this approach using 3-D simulations reveals more than 30% discrepancy in the 3 estimates of the off-current [10] which is most sensitive to multidimensional short channel effects.…”

Technology variability from a design perspective

“…Random device parameter fluctuations stem mainly from line-edge roughness (LER) [9], Si/SiO 2 and polysilicon (polySi) interface roughness [10] and random dopant fluctuations (RDF) [11].…”

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

“…Random device parameter fluctuations stem mainly from line-edge roughness (LER) [8], and polysilicon (poly-Si) interface roughness [9] and random dopant fluctuations (RDF) [10].…”