Technology variability from a design perspective

Abstract

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are reviewed in this paper. Transistor and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by padded-out cells and minimum operating voltages for the entire array. Correlations between various components of variability are essential for adding appropriate margins to the design.

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

“…Next, we consider when . is written as (30) is always positive so that is a positive-definite symmetric one. Therefore, is a positive-definite symmetric one.…”

“…Fig. 20 shows a word driver circuit, which is used in SRAM [28]- [30], TCAM [31], and flash memory. Here, the word driver circuit has ten blocks and one block has ten WLs.…”

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells

“…Although the advantages of ULV integrated circuits (ICs) have been widely promoted, designing ULV ICs is still challenging in the presence of technology variability [2], [3]. Compensating for on-chip variations (OCVs) is a tough task because OCVs are random and hard to be controlled using conventional corner-based methods.…”