Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements. A test chip is implemented in a 45 nm CMOS process. Large-scale SRAM read/write metrics are measured and compared against conventional SRAM stability metrics. Results show excellent correlation to conventional SRAM read/write metrics as well as V MIN measurements near failure.

Abstract-A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

Abstract-A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

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A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC.Introduction Increased process parameter variation has been perceived as one of the major roadblocks to further technology scaling. The corner-based design approach treats all variations as random. As the corner spread is increasing with technology scaling, simultaneously satisfying performance, power and yield requirements becomes challenging. In order to better account for the variability in the design process, it is necessary to distinguish systematic shifts in parameter values from truly random ones. The variations are generally characterized as within-die (WID), die-to-die (D2D) [1]. While these relationships are generally known at the process level, they are hardly visible to the designer.Test Chip The test chip, implemented in a general-purpose 90nm technology is used to evaluate the distributions of WID and D2D variations in ring oscillator frequencies and transistor standby leakage currents. The purpose of the experiment is to evaluate the absolute magnitude of WID and D2D variations, its spatial correlation, and the impact of layout styles. The chip contains an array of 10x16 tiles, occupying 1mm × 1mm area. Each tile has twelve 13-stage ring oscillators (ROs) and 12 transistors in the off-state, each with a different layout (Fig.1). The ring oscillators contain inverters with a single poly finger, as well as a stack of three fingers. Poly density, poly orientation and metal coverage are varied in the layout. To automate a large number of measurements, the RO frequency is divided down and its value is scanned out of the chip [2]. The tiles at the perimeter of the die are ignored in the measurements to eliminate edge effects. A single-slope ADC implemented using a high-gain folded-cascade amplifier with 2.5V devices, a large on-chip metal fringe capacitor and comparators was implemented on chip to measure transistor off-currents between 1nA to 1µA (Fig.2).Measurement Results Measured data shows three dominant and distinctive trends (Fig.3). The WID frequency variation for the same layout is small, up to 1.2% of the std. deviation/median (σ/µ). The systematic median frequency spread over RO layouts with different poly densities and orientations is much larger, up to 11.5%. This spread is significantly larger than 1.1% predicted by simulation of the extracted layout. Finally, the D2D spread is large, from a typical to a fast simulation corner. The ROs with single isolated poly fingers exceed the fast corner and are excluded from the measurements.Variations in stacked gates are less pronounced than those with single gates. Similarly, added poly stripes to maintain the uniform density reduce the variation effect as well. However the reduction in σ/µ of 0.3% is small, compared to a large reduction in average frequency of 11.5%.Spatial correlation ...

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Process variability in deeply scaled CMOS has both random and systematic components, with a varying degree of spatial correlation. A test chip has been built to study the effects of circuit layout on variability of delay and power dissipation in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC.

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