Technology Variability From a Design Perspective

Variability Effects in Graphene: Challenges and Opportunities for Device Engineering and Applications

“…It is instructive to compare the above-mentioned variability sources in graphene with those in silicon technology [42,43,46,[96][97][98][99]. Both Class I and II graphene variabilities are analogous to the random variations in silicon devices (i.e.…”

“…For example, some of Class I graphene variabilities (e.g. adsorbed molecules, surface roughness) are less problematic in silicon devices [43]. The variabilities near the graphene-dielectric/substrate interface have attracted considerable interest in graphene communities, mostly because they are 1) more influential in low-dimensional graphene devices with high surface-to-volume ratios [62,71], and 2) relatively less understood than the Si-SiO 2 interface in CMOS technology [52].…”

“…The variabilities near the graphene-dielectric/substrate interface have attracted considerable interest in graphene communities, mostly because they are 1) more influential in low-dimensional graphene devices with high surface-to-volume ratios [62,71], and 2) relatively less understood than the Si-SiO 2 interface in CMOS technology [52]. Moreover, Class II graphene variabilities are the randomness specific to the handling of graphene materials, which are not exactly the same as those in silicon devices [43,55,100,101]. For instance, edge disorders in graphene are not normally addressed in silicon devices possibly due to the maturity of CMOS technology.…”

“…limits the reliability and yield); addressing this issue requires optimization of both device and circuit designs [41][42][43][44][45][46][47]. Variability sources in the standard complementary metal-oxide-semiconductor (CMOS) process can be categorized according to their spatial characteristics, time-scales, physical/environmental origins and systematic/random components [42,43,46].…”

“…limits the reliability and yield); addressing this issue requires optimization of both device and circuit designs [41][42][43][44][45][46][47]. Variability sources in the standard complementary metal-oxide-semiconductor (CMOS) process can be categorized according to their spatial characteristics, time-scales, physical/environmental origins and systematic/random components [42,43,46]. And the nature of variability is likely to change with the progress of innovative materials, fabrication methods and device structures in the targeted applications [46,[48][49][50][51][52]: some variability sources may diminish while others may emerge; some can be minimized via device engineering (e.g.…”