Effect of thin-film imaging on line edge roughness transfer to underlayers during etch processes

Abstract

For the patterning of sub-100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, from a fundamental as well as a manufacturing perspective. With the migration to thin photoresists coupled with bottom antireflective coating (ARC)-hardmask underlayers, LER analysis of the developed resist structures is perhaps an inaccurate representation of the substrate roughness after the etch process, since those underlayers can play a significant role in increasing/decreasing linewidth variations during the image transfer process and hence can impact the device performance. In this article, atomic force microscopy is used to investigate the contribution of the imaging resist sidewall topography to the sidewall roughness of the final etched feature in thin photoresists, ARC, and hardmasks. Resist systems suitable for 248 and 193 nm lithography as well as fluorine-containing resists were processed using N2-H2 or fluorocarbon plasma etch. It is shown that the interaction of different etch chemistries with existing sidewall profiles can result in loss of the original morphological information and creation of new spatial frequency domains that act as physical templates for subsequent image transfer processes. Excessive roughness transfer into the hardmask layer due to insufficient resist thickness or inadequate etch resistance originates from striation propagation from the resist layer into the hardmask layer. In the case of fluorine-containing materials, a decreased etch resistance and reduced initial film thickness values give rise to critical underlayer roughening during plasma etch. Based on the results shown, it is predicted that advanced resist systems for 157 nm lithography and beyond will require the use of ARC layers with built-in hardmask properties in those particular cases in which patterning of deep trenches is needed, in order to maintain LER values within acceptable levels.

Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

“…In particular, it is reported that the etching process induces a smoother line edge in the LER profile [23]. Another study showed that the roughness distribution of the cross-section of multiply-etched stacks and the roughness of the edges is alleviated in the hard mask layer (inferred as longer correlation length) [24]. In addition, any thermal treatment such as soft bake or post-exposure bake would increase the correlation length of the LER profile, because of acid diffusion [25].…”

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

“…The variational surfaces of interconnects, for example, are modeled using spatially correlated Gaussian distribution in 3-dimensions, while the irregularity on different surfaces are usually considered independent based on the measurement data [6] [12]. Researches from the technology and the manufacturing part further indicate the nature of striations on the sidewalls [13] [14]. Thus it is appropriate to use the LER to model the sidewall variation of metal wires, as what will be done in this paper.…”

An analytical approach to efficient circuit variability analysis in scaled CMOS design

“…This variation is mainly affected by the process of gate etching, and is inherent to gate materials [23,7,14,12]. The concerning fact is that LER variation does not scale with technology and the improvement in the lithography process does not effectively reduce such an intrinsic variation.…”