Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

Abstract

A symmetric tunnel field-effect transistor (S-TFET) was recently proposed as an alternative device to address power density issues, featuring steep switching characteristic and bi-directional current flow with its symmetric structure. Because 193-nm immersion lithography is paired up with double or multiple patterning techniques for further enhancement of patterning resolution, the effect of double-patterning and double-etching (2P2E)-induced gate line-edge roughness (LER) [versus single-patterning and single-etching (1P1E)] on the S-TFET is investigated with various device design parameters. Finally, an investigation is conducted on the physical reasons which give rise to the difference in the LER parameters for 2P2E and 1P1E technique.

Optimization of spacer and source/channel junction to improve TFET characteristics

“…When a supply voltage (Vdd) is lowered for the low power applications, it is essential to lower a subthreshold swing (S) to maintain a high ON-state current (Ion) and a low OFF-state current (Ioff). However, as the metaloxide-semiconductor field-effect transistors (MOSFETs) cannot reduce S below 60 mV/dec at room temperature due to its fundamental limitations [1,2], several new devices such as positive feedback FETs [3,4], negative capacitance FETs (NCFETs) [5,6,7], nano-electro mechanical FETs (NEMFETs) [8,9] and tunnel FETs (TFETs) [10,11,12,13,14,15] are being explored as alternatives. Among them, TFETs are devices using band-to-band tunneling between source and channel as a current driving mechanism, and have received much attention because of those high compatibility with conventional complementary MOS (CMOS) processes [16,17].…”