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Physical phenomena underlying failure due to electromigration and stress-induced voiding in fine AI and AI-alloy thin-film conducting lines are examined in the context of accelerated testing methods and structures. Aspects examined include effects due to line isolation (the absence of reservoirs at conductor ends), solute and precipitate phenomena, conductor critical (Blech) length, microstructure, film deposition conditions, and thermal processing subsequent to film deposition. Emphasis is on the isolated, submicron-wide, AI(Cu)-based thin-film interconnection lines of IBM VLSI logic and memory chips. "Copyright 1995 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor.

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules.Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.