Reliability Wearout Mechanisms in Advanced CMOS Technologies

Strong, A.; Wu, Ernest Y.; Vollertsen, R.‐P.; Suñé, J.; Rosa, G. La; Sullivan, Timothy D.

doi:10.1002/9780470455265

Cited by 123 publications

(89 citation statements)

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“…Large scale studies of have already shown that existing processors are susceptible to error rates that are orders of magnitude higher than previously assumed [22]. Furthermore, leading technology experts warn that device robustness may decline even further for technology nodes below 32nm [6,34].…”

Section: Introductionmentioning

confidence: 99%

Viper: Virtual pipelines for enhanced reliability

Pellegrini¹,

Greathouse²,

Bertacco³

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device reliability is a secondary concern. As the rate of permanent hardware faults increases, robustness will become a first class constraint for even low-cost systems. Current research into reliable architectures has focused on ad-hoc solutions to improve designs without altering their centralized control logic. Unfortunately, this centralized control presents a single point of failure, which limits long-term robustness.To address this issue, we introduce Viper, an architecture built from a redundant collection of fine-grained hardware components. Instructions are perceived as customers that require a sequence of services in order to properly execute. The hardware components vie to perform what services they can, dynamically forming virtual pipelines that avoid defective hardware. This is done using distributed control logic, which avoids a single point of failure by construction.Viper can tolerate a high number of permanent faults due to its inherent redundancy. As fault counts increase, its performance degrades more gracefully than traditional centralized-logic architectures. We estimate that fault rates higher than one permanent faults per 12 million transistors, on average, cause the throughput of a classic CMP design to fall below that of a Viper design of similar size.

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Section: Introductionmentioning

confidence: 99%

Viper: Virtual pipelines for enhanced reliability

Pellegrini¹,

Greathouse²,

Bertacco³

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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show abstract

“…Many academic experts, industry consortia and research panels have warned that future generations of silicon technology are likely to be significantly less reliable [56]. A recent exascale study [6] and the Computing Community Consortium Visioning Study [1] conclude that handling reliability will probably become a first-order constraint.…”

Section: Introductionmentioning

confidence: 99%

Mechanisms and Evaluation of Cross-Layer Fault-Tolerance for Supercomputing

Kruijf

Sankaralingam

et al. 2012

2012 41st International Conference on Parallel Processing

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Abstract-Reliability is emerging as an important constraint for future microprocessors. Cooperative hardware and software approaches for error tolerance can solve this hardware reliability challenge. Cross-layer fault tolerance frameworks expose hardware failures to upper-layers, like the compiler, to help correct faults. Such cooperative approaches require less hardware complexity than masking all faults at the hardware level and are generally more energy efficient.This paper provides a detailed design and an implementation study of cross-layer fault tolerance for supercomputing. Since supercomputers necessarily involve large component counts, they have more frequent failures than consumer electronics and small systems. Conventionally, these systems use redundancy and checkpointing to achieve reliable computing. However, redundancy increases acquisition as well as recurring energy costs. This paper describes a simple language-level mechanism coupled with complementary compilation and lightweight hardware error detection that provides efficient reliability and cross-layer faulttolerance for supercomputers. Our evaluation focuses on strong scaling problems for which we can trade computing power for redundancy. Our results show a range of 1.07x to 2.5x speedup when employing cross-layer error-tolerance compared to conventional full dual modular redundancy (DMR) to contain all errors within hardware. Further, we demonstrate the approach can sustain 7% to 50% lower energy. The most important result of this work is qualitative: we can use a simplified hardware design with relaxed architectural correctness guarantees.

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“…Unfortunately, according to several experts, reliability is a major obstacle that can jeopardize this growth. Indeed, as transistor dimensions reduce, their susceptibility to both transient and permanent faults is expected to increase significantly, causing failures in deployed systems [30].…”

Section: Introductionmentioning

confidence: 99%

Cardio: Adaptive CMPs for reliability through dynamic introspective operation

Pellegrini

Bertacco

2011

2011 IEEE International High Level Design Validation and Test Workshop

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Abstract-Current technology scaling enables the integration of tens of processing elements into a single chip, and future technology nodes will soon allow the integration of hundreds of cores per device. While very powerful, many experts agree that these systems will be prone to a significant number of permanent and transient faults during their lifetime. If not properly handled, effects of runtime failures can be dramatic.In this work, we propose Cardio, a distributed architecture for reliable chip multiprocessors. Cardio, a novel approach for onchip reliability is based on hardware detectors that spot failures and on software routines that reorganize the system to work around faulty components. Compared to previous online reliability solutions, Cardio provides failure reactivity comparable to hardware-only reliable solutions while requiring a much lower area overhead. Cardio operates a distributed resource manager to collect health information about components and leverages a robust distributed control mechanism to manage system-level recovery. Our architecture operational as long as at least one general purpose processor is still functional in the chip. We evaluated our design using a custom simulator and estimate its runtime impact on the SPECMPI benchmarks to be lower than 3%. We estimate its dynamic reconfiguration time to be comprised between 20 and 50 thousand cycles per failure.

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Reliability Wearout Mechanisms in Advanced CMOS Technologies

Cited by 123 publications

References 0 publications

Viper: Virtual pipelines for enhanced reliability

Viper: Virtual pipelines for enhanced reliability

Mechanisms and Evaluation of Cross-Layer Fault-Tolerance for Supercomputing

Cardio: Adaptive CMPs for reliability through dynamic introspective operation

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