3D copper TSV integration, testing and reliability

Farooq, Mukta; Graves-Abe, Troy; Landers, W.; Kothandaraman, C.; Himmel, Ben; Andry, Paul; Tsang, C. K.; Sprogis, E.; Volant, R.; Petrarca, K.; Winstel, Kevin; Safran, J.; Sullivan, Timothy D.; Chen, F.; Shapiro, M. J.; Hannon, R.; Liptak, R. W.; Berger, D.; Iyer, Subramanian S.

doi:10.1109/iedm.2011.6131504

Cited by 99 publications

(34 citation statements)

References 7 publications

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“…The IR interferometer and total thickness gauges measured silicon substrates of known thickness as certified by an accredited third party and were compared. The via-middle process scheme for TSV 3DIC fabrication holds significant interests from the semiconductor industry [1]. In this scheme, blind vias are fabricated on the deviceside of TSV wafers after completing the front-end processes.…”

Section: Measurement Using Ir Reflectancementioning

confidence: 99%

A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal

Alvanos¹,

Garant

Iijima³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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As 3DIC with through silicon vias (TSV) approaches high volume manufacturing readiness the importance of precision backgrinding has become increasingly more evident. Active management of the backgrinding process has multiple benefits in that it reduces the risk of wafer backside contamination due to premature contact with vias, it enables optimization of the post-thinning residual silicon thickness and the final via reveal process. It can compensate for poor via fabrication depth uniformity and less than ideal temporary bonding total thickness variation (TTV). In this paper we will demonstrate the utility of two tools that when used together can systematically produce thin TSV containing wafers to their optimal thickness while protecting the wafers from particulate contamination. The first instrument in this process scheme is a metrology tool that utilizes IR reflectance to measure the silicon thickness remaining between the bottom of the TSV and backside surface of the wafer. These measurements are then transferred to a special grinding tool that can interpret the data and make changes to the grinding depth within the wafer so as to leave thickness of silicon above the TSVs as uniform as possible. Having removed the bulk of the Si through mechanical grinding and Chem/Mech polishing, the next step in the via-middle process is to remove the last few microns of Si overburden to expose the vias. By leaving a shallower Si layer above the TSV during the thinning process compared to current process, the final via reveal process time can be reduced. Also the need for rework in this process because of the wafer-to-wafer variability in the remaining silicon thickness above the TSV can be eliminated. In addition to measuring the pre-grinding Si thickness, the IR reflectance measurement tool can be used to verify the remaining silicon thickness post grind, establishing thinning process feedback and via reveal process feed-forward data.

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Section: Measurement Using Ir Reflectancementioning

confidence: 99%

A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal

Alvanos¹,

Garant

Iijima³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…In order to understand and mitigate thermal fatigue concerns in Cu TSV interconnects, many studies have been reported that have assessed the thermal cycling effect on their reliability performance [2], [3], [4], [5]. These reported studies were focused on understanding how thermal cycling impacts the electrical characteristics of Cu TSVs, as well as the use of focused ion beam (FIB) and scanning electron microscopy (SEM) failure analysis tools to identify damage growth and propagation.…”

Section: Introductionmentioning

confidence: 98%

X-ray micro-beam diffraction measurement of the effect of thermal cycling on stress in Cu TSV: A comparative study

Okoro

Levine

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Microelectronic devices are subjected to constantly varying temperature conditions during their operational lifetime, which can lead to their failure. In this study, we examined the impact of thermal cycling on the evolution of stresses in Cu TSVs using synchrotron-based X-ray microdiffraction. Two test conditions were analyzed: as-received and 1000 cycled samples. The principal and shear stresses in the 1000 cycled sample were five times greater than in the asreceived sample. This was attributed to the increased strain hardening upon thermal cycling. The variation in stresses with thermal cycling is a clear indication that the impact of Cu TSV proximity on front-end-of-line (FEOL) device performance will fluctuate throughout the lifetime of the 3D stacked dies, and thus should be accounted for during FEOL keep-out-zone design rule development. INTRODUCTIONStress-related reliability challenges are known to be one of the main causes of failure in electronic devices. This failure type arises due to the mismatch in the mechanical properties of the constituent materials. One of the causes of stressrelated failures is the continuous fluctuation of temperature in microelectronic devices during their in-service usage [1]. This leads to thermal fatigue occurrence, and subsequently to failure.The emergence of three-dimensional stacked integrated circuits further increases the risk of thermal fatigue failures. This is because the electrical connection between the stacked dies are achieved using mainly Cu through-silicon vias (TSVs), which are fabricated through the active silicon. The large dissimilarity in the material properties of the Cu TSV and the surrounding Si can result in huge stresses.In order to understand and mitigate thermal fatigue concerns in Cu TSV interconnects, many studies have been reported that have assessed the thermal cycling effect on their reliability performance [2], [3], [4], [5]. These reported studies were focused on understanding how thermal cycling impacts the electrical characteristics of Cu TSVs, as well as the use of focused ion beam (FIB) and scanning electron microscopy (SEM) failure analysis tools to identify damage growth and propagation. However, no reported study has been able to experimentally relate the underlying root cause of the changes in the Cu TSV, being the buildup of stresses, with the witnessed number of thermal cycles.

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“…What follows is a brief summary of the motivation for why those particular methods have been preferred. First, via-first [8]- [10] and viamiddle [11], [12] type TSVs can only be fabricated in a CMOS foundry. Therefore, via-last approach is preferred to develop 3-D prototypes in a MEMS clean room after the pretesting and selection of working chips (known-good-die or KGD).…”

Section: Introductionmentioning

confidence: 99%

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Temiz

Guiducci

Leblebici

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Abstract-This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spincoated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process. In this paper, two 50-μm-thick chips were post-processed, aligned, bonded, and connected by Cu TSVs, which have parylene sidewall passivation. Daisy-chain resistance measurements show 0.5-resistance on average for 60-μm-diameter TSVs, with a yield of more than 99% for 1280 TSVs from five different chip stacks. Subsequently, the techniques were applied to CMOS microprocessor stacking as a test vehicle. Die-level post-CMOS processing for 40-μm-diameter via etching, redistribution layer patterning, and chip-to-chip bonding were successfully demonstrated with the real chips.Index Terms-3-D integration, die-level processing, dry-film lithography, parylene bonding, post-complementary metal oxide semiconductor (CMOS) processing, through-silicon via (TSV), via-last TSV.

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3D copper TSV integration, testing and reliability

Cited by 99 publications

References 7 publications

A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal

A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal

X-ray micro-beam diffraction measurement of the effect of thermal cycling on stress in Cu TSV: A comparative study

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

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