Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Abstract

Abstract-This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spincoated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process. In this paper, two 50-μm-thick chips were post-processed, aligned, bonded, and connected by Cu TSVs, which have parylene sidewall passivation. Daisy-chain resistance measurements show 0.5-resistance on average for 60-μm-diameter TSVs, with a yield of more than 99% for 1280 TSVs from five different chip stacks. Subsequently, the techniques were applied to CMOS microprocessor stacking as a test vehicle. Die-level post-CMOS processing for 40-μm-diameter via etching, redistribution layer patterning, and chip-to-chip bonding were successfully demonstrated with the real chips.Index Terms-3-D integration, die-level processing, dry-film lithography, parylene bonding, post-complementary metal oxide semiconductor (CMOS) processing, through-silicon via (TSV), via-last TSV.

‘Chip-olate’ and dry-film resists for efficient fabrication, singulation and sealing of microfluidic chips

“…DFRs were developed as potential replacement for photoresists that are deposited by spin-coating: unlike their liquid counterparts (e.g. SU-8), DFRs are solid and available as rolls with typical thicknesses of the foil ranging from 5 µm to 100 µm (thicker layers can be obtained by multiple deposition) and length of up to 100 m. DFRs are meant to be laminated while applying some heat, exposed, developed, and post-baked [28,29]. DFRs were previously employed in the fabrication of microfluidic systems [19,21,[30][31][32]; however, these studies did not address the challenges of chip singulation, contamination of closed microchannels, high-throughput surface cleaning and treatment, and compatibility with integration of reagents.…”

Metrology for Monitoring and Detecting Process Issues in a TSV Module

“…As an approach to enhance integrated chip performance and achieve high-density functionality, 3D integration schemes have received considerable attention during the past years by many research teams in both academia and industry, and various concepts are being explored as well as process routes extended. [1][2][3] When designing new processes for use in 3D integration, the availability and new development of metrology is an important prerequisite for an eventual successful adoption by the industry. 4 In this work, deviations from the standard recipes of unit processes in a TSV module are deliberately introduced and various types of metrology have been applied with the goal of exploring their detection capabilities as well as limitations.…”