As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single-and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

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In this paper, the reliability of through-silicon via (TSV) daisy chains under thermal cycling conditions was examined. The electrical resistance of TSV daisy chains was found to increase with the number of thermal cycles, due to thermally induced damage leading to the formation and growth of defects. The contributions of each identified damage type to the change in the electrical resistance of the TSV chain were evaluated by electrical modeling. Thermo-mechanical modeling showed a good correlation between the observed damage locations and the simulated stress-concentration regions of the TSV.Index Terms-Failure analysis, finite element analysis, threedimensional integrated circuits, through-silicon vias.

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In this paper, the effect of annealing condition on the microstructural and mechanical behavior of copper through-silicon via (Cu-TSV) is studied. The hardness of Cu-TSV scaled with the Hall–Petch relation, with the average hardness values of 1.9 GPa, 2.2 GPa and 2.3–2.8 GPa, respectively for the annealed, room temperature (RT) aged and the as-deposited samples. The increase in hardness toward the top of the as-deposited sample is related to the decrease in grain size. The annealed and the as-deposited samples showed a constant elastic modulus (E-modulus) value across the length of Cu-TSV of 140 GPa and 125 GPa respectively, while the RT aged sample showed a degradation in E-modulus from the bottom of the TSV (140 GPa) to the top (110 GPa). These differences in E-modulus values and trends under the different test conditions were found to be unrelated with the crystallographic texture of the samples, but could be related to the presence of residual stresses. No correlation is found between the hardness and E-modulus data. This is attributed to the coupling and competitive effects of grain size and residual stresses, with the grain size effect having a dominant influence on hardness, while the presence of residual stresses dominated the E-modulus result.

In this paper, we discuss the use of low frequency (up to 300 MHz) radio waves (RF) to detect and characterize electrical defects present in the dielectrics of emerging integrated circuit devices. As an illustration, the technique is used to monitor the impact of thermal cycling on the RF signal characteristics (S-parameters, such as S11 and S21) of electrically active defects in three dimensional (3D) interconnects. The observed changes in the electrical characteristics of the interconnects were traced to changes in the chemistry of the isolation dielectric used in the through silicon via (TSV) construction; specifically to the conversion of chemical intermediates such as non-bridging silanol (Si-OH) to bridging siloxane (Si-O-Si). We suggest that these “chemical defects” inherent in the ‘as-manufactured’ products may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices. This low frequency RF technique could be optimized to complement, and in some cases compete favorably with, other thin film metrology techniques, such as ellipsometry and Fourier transform infrared spectroscopy (FTIR), for mass production environments.

Nondestructive measurements of the full elastic strain and stress tensors from individual dislocation cells distributed along the full extent of a 50 mm-long polycrystalline copper via in Si is reported. Determining all of the components of these tensors from sub-micrometre regions within deformed metals presents considerable challenges. The primary issues are ensuring that different diffraction peaks originate from the same sample volume and that accurate determination is made of the peak positions from plastically deformed samples. For these measurements, three widely separated reflections were examined from selected, individual grains along the via. The lattice spacings and peak positions were measured for multiple dislocation cell interiors within each grain and the cell-interior peaks were sorted out using the measured included angles. A comprehensive uncertainty analysis using a Monte Carlo uncertainty algorithm provided uncertainties for the elastic strain tensor and stress tensor components.

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