Accelerated Stress Test Assessment of Through-Silicon Via Using RF Signals

IEEE Trans. Electron Devices

Lau

Golshany

et al. 2014

Self Cite

In this paper, the reliability of through-silicon via (TSV) daisy chains under thermal cycling conditions was examined. The electrical resistance of TSV daisy chains was found to increase with the number of thermal cycles, due to thermally induced damage leading to the formation and growth of defects. The contributions of each identified damage type to the change in the electrical resistance of the TSV chain were evaluated by electrical modeling. Thermo-mechanical modeling showed a good correlation between the observed damage locations and the simulated stress-concentration regions of the TSV.Index Terms-Failure analysis, finite element analysis, threedimensional integrated circuits, through-silicon vias.

Section: Discussionmentioning

confidence: 66%

Section: Introductionmentioning

confidence: 93%

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A Detailed Failure Analysis Examination of the Effect of Thermal Cycling on Cu TSV Reliability

IEEE Trans. Electron Devices

Lau

Golshany

et al. 2014

Self Cite

“…These differences are not artefacts of the measurement; they were observed on several samples using the same calibration procedure. Similar changes in RF scattering with thermal cycling have been described in detail elsewhere 2,19 but for the purposes of this report, we focus on the changes occurring at the low frequency (< 300MHz) end of the spectrum. That the dispersion in both transmission and reflection coefficients disappears after 500 thermal cycles suggests transformation in the materials of construction with heat-treatment.…”

Section: Methodsmentioning

confidence: 74%

Low Frequency Radio Wave Detection of Electrically Active Defects in Dielectrics

Obeng

ECS J. Solid State Sci. Technol.

Amoah

et al. 2015

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In this paper, we discuss the use of low frequency (up to 300 MHz) radio waves (RF) to detect and characterize electrical defects present in the dielectrics of emerging integrated circuit devices. As an illustration, the technique is used to monitor the impact of thermal cycling on the RF signal characteristics (S-parameters, such as S11 and S21) of electrically active defects in three dimensional (3D) interconnects. The observed changes in the electrical characteristics of the interconnects were traced to changes in the chemistry of the isolation dielectric used in the through silicon via (TSV) construction; specifically to the conversion of chemical intermediates such as non-bridging silanol (Si-OH) to bridging siloxane (Si-O-Si). We suggest that these “chemical defects” inherent in the ‘as-manufactured’ products may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices. This low frequency RF technique could be optimized to complement, and in some cases compete favorably with, other thin film metrology techniques, such as ellipsometry and Fourier transform infrared spectroscopy (FTIR), for mass production environments.

“…In order to understand and mitigate thermal fatigue concerns in Cu TSV interconnects, many studies have been reported that have assessed the thermal cycling effect on their reliability performance [2], [3], [4], [5]. These reported studies were focused on understanding how thermal cycling impacts the electrical characteristics of Cu TSVs, as well as the use of focused ion beam (FIB) and scanning electron microscopy (SEM) failure analysis tools to identify damage growth and propagation.…”

Section: Introductionmentioning

confidence: 99%

X-ray micro-beam diffraction measurement of the effect of thermal cycling on stress in Cu TSV: A comparative study

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

Levine

et al. 2014

Self Cite

Microelectronic devices are subjected to constantly varying temperature conditions during their operational lifetime, which can lead to their failure. In this study, we examined the impact of thermal cycling on the evolution of stresses in Cu TSVs using synchrotron-based X-ray microdiffraction. Two test conditions were analyzed: as-received and 1000 cycled samples. The principal and shear stresses in the 1000 cycled sample were five times greater than in the asreceived sample. This was attributed to the increased strain hardening upon thermal cycling. The variation in stresses with thermal cycling is a clear indication that the impact of Cu TSV proximity on front-end-of-line (FEOL) device performance will fluctuate throughout the lifetime of the 3D stacked dies, and thus should be accounted for during FEOL keep-out-zone design rule development. INTRODUCTIONStress-related reliability challenges are known to be one of the main causes of failure in electronic devices. This failure type arises due to the mismatch in the mechanical properties of the constituent materials. One of the causes of stressrelated failures is the continuous fluctuation of temperature in microelectronic devices during their in-service usage [1]. This leads to thermal fatigue occurrence, and subsequently to failure.The emergence of three-dimensional stacked integrated circuits further increases the risk of thermal fatigue failures. This is because the electrical connection between the stacked dies are achieved using mainly Cu through-silicon vias (TSVs), which are fabricated through the active silicon. The large dissimilarity in the material properties of the Cu TSV and the surrounding Si can result in huge stresses.In order to understand and mitigate thermal fatigue concerns in Cu TSV interconnects, many studies have been reported that have assessed the thermal cycling effect on their reliability performance [2], [3], [4], [5]. These reported studies were focused on understanding how thermal cycling impacts the electrical characteristics of Cu TSVs, as well as the use of focused ion beam (FIB) and scanning electron microscopy (SEM) failure analysis tools to identify damage growth and propagation. However, no reported study has been able to experimentally relate the underlying root cause of the changes in the Cu TSV, being the buildup of stresses, with the witnessed number of thermal cycles.