Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120-300 nm have been studied as room temperature plasma wave detectors of 0.7 THz electromagnetic radiation. In agreement with the plasma wave detection theory, the response was found to depend on the gate length and the gate bias. The obtained values of responsivity (<= 200 V/W) and noise equivalent power (>= 10(-10) W/Hz(0.5)) demonstrate the potential of Si MOSFETs as sensitive detectors of terahertz radiation. (c) 2006 American Institute of Physics

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This paper investigates terahertz detectors fabricated in a low-cost 130 nm silicon CMOS technology. We show that the detectors consisting of a nMOS field effect transistor as rectifying element and an integrated bow-tie coupling antenna achieve a record responsivity above 5 kV/W and a noise equivalent power below 10 pW/Hz(0.5) in the important atmospheric window around 300 GHz and at room temperature. We demonstrate furthermore that the same detectors are efficient for imaging in a very wide frequency range from ~0.27 THz up to 1.05 THz. These results pave the way towards high sensitivity focal plane arrays in silicon for terahertz imaging.

We report on experiments on photoresponse to sub-THz ͑120 GHz͒ radiation of Si field-effect transistors (FETs) with nanometer and submicron gate lengths at 300 K. The observed photoresponse is in agreement with predictions of the Dyakonov-Shur plasma wave detection theory. This is experimental evidence of the plasma wave detection by silicon FETs. The plasma wave parameters deduced from the experiments allow us to predict the nonresonant and resonant detection in THz range by nanometer size silicon devices-operating at room temperature.

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A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guarantied by epitaxial process. The SON process allows the buried dielectric (which may be an oxide but also an air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.