The end of CMOS scaling

Skotnicki, T.; Hutchby, J.A.; King, Tsu‐Jae; Wong, H.-S. Philip; Bœuf, F.

doi:10.1109/mcd.2005.1388765

Cited by 381 publications

(107 citation statements)

References 70 publications

Supporting

Mentioning

102

Contrasting

Order By: Relevance

“…1,2 The major bottlenecks are the short-channel effects and the inability to reduce the operation voltage. 3 In recent years, there has been a drive to explore new channel materials that can conceivably extend conventional device scaling.…”

mentioning

confidence: 99%

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

Tulevski²,

Hannon³

et al. 2015

Applied Physics Letters

View full text Add to dashboard Cite

show abstract

mentioning

confidence: 99%

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

Tulevski²,

Hannon³

et al. 2015

Applied Physics Letters

View full text Add to dashboard Cite

show abstract

“…But as a result, the influence of the drain on the channel also competes more and more with that of the gate, leading to the occurring of SCEs with an increased leakage current, degraded subthreshold swing and a reduced output resistance. For shorter channel c-Si MOSFETs, making thinner gate dielectric layer is important to maintain the strong electrostatic control of the channel from the gate, and various junction and doping technologies such as ultra-shallow junctions, halo implantation and lightly doped source/drain are also introduced to provide SCE suppression (14). Contrarily, for TFTs, it is very difficult to process high quality and very thin dielectric layer efficiently with high yield over large areas, and complicated junction and doping technologies are also not applicable.…”

Section: Device Structures To Suppress Short-channel Effectsmentioning

confidence: 99%

Down-scaling of Thin-Film Transistors: Opportunities and Design Challenges

et al. 2009

View full text Add to dashboard Cite

With the ever-increasing demands for integration of advanced electronic functions into large-area electronics, down-scaling of thin-film transistors (TFTs) becomes very necessary. The key device operational issues associated with TFT scaling, including short-channel effects (SCEs) and self-heating, are considered in this paper. Device structure engineering approaches are introduced to suppress the SCEs for designing short-channel TFTs with excellent digital and analog performance. And electro-thermal simulation results show that the self-heating in TFTs will be much more significant than that in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the substrate of poor thermal conductivity. Enhancing the heat dissipation by placement of metal heat pipes in the cap dielectric layers is proved to be an effective way to deal with the heating issues.

show abstract

“…In this modern world of technology, where unlimited functions need to be done using limited resources so a lot ofresources and work force is devoted to miniaturization of a transistor so-called "Scaling" [1] Scaling affects the density, speed, functionality, power dissi-pation and cost of an IC [2,3] According to Moore's law transistor is considered as a fundamental element of a digital IC. Now a days scaling reachedpractical limits where it cannot retains the original characteristic due to the presence of short channel effects(SCEs).Due to SCEs devices power dissipation increases.…”

Section: Introductionmentioning

confidence: 99%