Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

“…This is because the DIBL effect is smaller in a long channel or well-tempered devices. These observations also agree with the voltage-doping transformation theory proposed by Skotnicki et al [17]. For transistor with finger number of 48, significant increases of subthreshold slope was found.…”

“…Under this situation, the subthreshold slope is mainly determined by the depletion capacitance and the interface trap density which should have little variation as long as the total gate widths are the same. The results agree with the theory predicted by Skotnicki et al [17]. However, for 90-nm long transistors, the subthreshold slope decreases as the gate number of finger increases.…”

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

“…An intuitive expression as indicator for a good transistor is the simple approximation called the electrostatic integrity (EI) as given below [13]:…”

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

“…Low power in standby mode (LSTP) technologies nominal threshold voltage is large and thus their SCE, DIBL and S are required to be much better than those of HP technologies. The lowoperating-power technology (LOP) requires speed in the active mode and low power in the standby mode [39]. Considering the three big families of products as high performance (HP), low operational power (LOP), and low standby power (LSTP), a roadmap is created as a ready reckoner for sub micron and deep submicron devices in Tables 2 and 3.…”