On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Wong, Hei; Iwai, Hiroshi

doi:10.1016/j.mee.2015.02.023

Cited by 50 publications

(38 citation statements)

References 47 publications

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“…The anomalous large current could not be explained with any other conduction mechanism for this situation. As the interface La 2 O 3 /silicon has a small conduction band offset and as the effective mass of electrons in the conduction band is reduced, it was estimated that the direct tunneling limit is just slightly below 5 nm [ 2 ]. Although the thermal annealing at 300 °C should not cause significant interface growth, this process is still able to make both the top and bottom interfaces rougher.…”

Section: Resultsmentioning

confidence: 99%

“…The continual downsizing process of CMOS devices has been slowed down in recent years due to difficulties encountered when approaching both physical and technological limits, which are believed to be of a couple of nanometers in feature size [ 1 , 2 ]. The technological limits can be split into two different categories.…”

Section: Introductionmentioning

confidence: 99%

“…One group refers to the minimum achievable dimensions such as the fin width in a FinFET structure or the diameter of a silicon nanowire in a gate-all-around (GAA) structure. These limits are not only governed primarily by the available lithography techniques, but also by the gate dielectric thickness in the sense of equivalent oxide thickness (EOT), which is limited by the thin layer deposition techniques and by some other processing steps that may result in the EOT degradation [ 2 ]. However, as device gate length being scaled to a few nanometers and the gate dielectric thickness approaching the atomic scale, it is expected that the thickness fluctuation of the gate dielectric, the surface roughness on the fins in the FinFET structure or on the nanowire in the Gate-All-Around (GAA) structure, the gate dielectric/silicon interface and the gate dielectric/metal gate interface could become comparable to the gate dielectric thickness itself [ 3 , 4 ].…”

Section: Introductionmentioning

confidence: 99%

“…Thanks to the introduction of high-k materials, the physical thickness of the gate dielectric is now still maintained well above the atomic scale for the current nano CMOS technology [ 2 ]. When the EOT gate dielectric is further scaled down to a half nanometer range, the surface roughness fluctuation of this ultrathin film will become a serious issue and particular cares need to be taken in the process design and the device variability control [ 4 , 5 ].…”

Section: Introductionmentioning

confidence: 99%

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Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices

2021

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As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La2O3/Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La2O3/Si interface and the interface reactions at the W/La2O3 interface. The surface roughness effects are expected to be severe in future generations’ devices with even thinner gate dielectric film and smaller size of the devices.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices

2021

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“…This tri-layers channel based structure on 45nm channel length compared with HOI MOSFET developed by Khiangte et.al. Equal potential is applied on each gate having same work function so that equal depletion region is created in the tri-layered channel resulting in lowering of the electric field penetration with minimal short channel effects [12][13][14]. The doping dependence model Shockley Read Hall recombination [15 -17] and strain induces based piezo-restive model [18] are incorporated in device simulation to investigate strain effect on electron velocity and drift velocity of electrons in tri-layered channel.…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

2019

IJITEE

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The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.

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Electrodes for High‐𝜅 Molecular Crystal Antimony Trioxide Gate Dielectrics for 2D Electronics

Ranjan,

Zeng,

Olsson

2024

Adv Elect Materials

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Wafer‐scale deposition of high‐𝜅 gate dielectrics compatible with atomically thin van der Waals layered semiconductors (e.g., MoS2, WS2, WSe2) is urgently needed for practical applications of field effect transistors based on 2D materials. A study on a high‐𝜅 molecular crystal antimony trioxide (Sb2O3) gate dielectric examined the role of electrode material on dielectric degradation and breakdown. It is demonstrated that the thin films of Sb2O3 can be uniformly deposited on a wafer scale. The current–voltage (I–V) curves show tightly controlled distributions of both leakage current and breakdown voltage. Electrical measurements reveal that defects are generated gradually upon electrical stressing. The evaluation of degradation is based on charge trapping, stress‐induced leakage current, and dielectric breakdown measurements. The breakdown voltage distribution follows a tight monomodal Weibull distribution suggesting a high quality of the film. Comparing Ti and Au as gate electrodes, both the breakdown field and the tunnel current are affected by the choice of electrode material. Transmission electron microscopy reveals that the chemistry at the electrode/Sb2O3 interface plays an important role and that Ti scavenges oxygen from the Sb2O3, forming a defective oxide layer at the Ti/Sb2O3 interface. For the Au electrode, this interfacial reaction is completely absent, improving the dielectric performance.

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On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Cited by 50 publications

References 47 publications

Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices

Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

Electrodes for High‐𝜅 Molecular Crystal Antimony Trioxide Gate Dielectrics for 2D Electronics

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