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We review the salient aspects of nanoimprint lithography and consider the challenges it faces in becoming a standard fabrication technique, such as costs and throughput. We discuss material issues such as visco-elasticity and functionality of the printed material. By way of an illustration, we present printing results of 50 nm features over a 2×2 cm2 area which are reproducible with high fidelity. Data of printing 15 nm features in PMMA using a Cr stamp was obtained.

A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

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We have tested nanoimprint lithography, a new and promising technique for nanometer-scale pattern definition. Preliminary experiments reveal that, besides severe sticking and adhesion problems, the problem of material transport is one inherent to this technique. There are clear indications that most of the effects found may be understood in terms of material transport. We performed experiments within a well defined pressure and temperature window which ranged from 60 to 100 bar and from 50 to 90 °C above the glass transition temperature of the poly(methylmethacrylate)-like polymer used. As a result, the quality of imprint is evaluated with respect to full area pattern transfer, based on a qualitative scanning electron microscope investigation of the fully imprinted area of 2 cm × 2 cm patterned with features of different size and shape. Optimum conditions for imprint quality are found around 100 bar and 90 °C above Tg for the specific polymer used. Although material transport will limit nanoimprint performance in general, it is found that periodic patterns and isolated or small area negative stamp relief patterns are most suitable for high quality nanoimprinting.