The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four
Approximate Full Adders
(AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an
N
-bit approximate adder that hereinafter is referred as “ApproxADD.” An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay (
O
(1)). ApproxADD also provides improvement in dynamic power consumption by 46.31% and in area by 28.57% w.r.t.
Ripple Carry Adder
(RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i)
Error Distance
(ED) is too high; and (ii)
Error Rate
(ER) increases rapidly with bit-width (
N
). To improve ED and ER, we exploit the concept of
carry-lifetime
and
Error Detection and Correction
logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD
υ
1 and ApproxADD. We call these as ApproxADD
υ
1 and ApproxADD
υ
2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in
Discrete Cosine Transform
(DCT) and
Inverse Discrete Cosine Transform
(IDCT) modules with ApproxADD
υ
2.
In the majority of Digital Signal Processing (DSP) applications, such as image, audio and video processing, the final result is interpreted by human senses; and, the fact of confined perception of human senses declines the strict restriction on accuracy. Thus, by adopting the emerging concept of approximate computing, we propose an approximate radix-2 hybrid redundant Multiply-and-Accumulate (ApproxMAC) unit which stems a novel Speed-Power-Accuracy-Area (SPAA) metrics. The Approx-MAC unit attains tremendous improvements in computational performance, energy efficiency and silicon area with a trivial degradation in the output quality. To inspect the effectiveness of the proposed approach in real-time DSP applications, we demonstrate an ApproxMAC unit embedded JPEG-E-X IP core architecture. The ApproxMAC unit with 40 approximate LSBs ensures 7.177× and 1.526× speedup, 1.594× and 4.163× energy efficiency, and 1.131× and 1.277× silicon area improvements over binary and hybrid redundant MAC units, respectively. Moreover, the ApproxMAC unit with 40 approximate LSBs decorates powerprecision and delay-precision metrics by 14.71% and 32.95%, respectively.
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