In the majority of Digital Signal Processing (DSP) applications, such as image, audio and video processing, the final result is interpreted by human senses; and, the fact of confined perception of human senses declines the strict restriction on accuracy. Thus, by adopting the emerging concept of approximate computing, we propose an approximate radix-2 hybrid redundant Multiply-and-Accumulate (ApproxMAC) unit which stems a novel Speed-Power-Accuracy-Area (SPAA) metrics. The Approx-MAC unit attains tremendous improvements in computational performance, energy efficiency and silicon area with a trivial degradation in the output quality. To inspect the effectiveness of the proposed approach in real-time DSP applications, we demonstrate an ApproxMAC unit embedded JPEG-E-X IP core architecture. The ApproxMAC unit with 40 approximate LSBs ensures 7.177× and 1.526× speedup, 1.594× and 4.163× energy efficiency, and 1.131× and 1.277× silicon area improvements over binary and hybrid redundant MAC units, respectively. Moreover, the ApproxMAC unit with 40 approximate LSBs decorates powerprecision and delay-precision metrics by 14.71% and 32.95%, respectively.
Wireless network is a growing technology that facilitates users for sharing of information instantly through wireless electronic devices irrespective of their locations. It can be infrastructure based or infrastructure less (ad hoc networks). An ad hoc network gains more attention because of its convenience, mobility, scalability, cost and easy setup. It is best suitable for applications, where predefined infrastructure is not possible. But ad hoc network is vulnerable to various attacks due to its functionality and deployment scenario. It is a decentralized networks therefore all the routing activities are handled by nodes. Nodes may behave badly in the network and can drop the packets instead of forwarding them. The aim of this research work is to detect these packet dropping nodes in MANET and prevents these packet droppers to be chosen as an active element of the path used for packet forwarding in DSR (Dynamic Source Routing) protocol. For this, we have implemented a trust and cluster based monitoring technique and simulated this environment using network simulator NS2.
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Variations in process parameter jeopardize the parametric yield which imposes severe cost implication on the semiconductor industry. Post-silicon tunning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) is a powerful technique that mitigates the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, to enhance the parametric yield, we integrate ABB and DVS for the Hybrid Redundant Multiply-andAccumulate (HR-MAC) units. Simulation results based on the PTM 32nm CMOS technology show that the proposed approach enhances the parametric yield at Fast-Fast (FF), Fast-Slow (FS), Slow-Fast (SF) and Slow-Slow (SS) process corners by 81.5%, 45.3%, 59.92% and 89.08%, respectively.
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