A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications

Dutt, Sunil; Chauhan, Anshu; Bhadoriya, Rahul; Nandi, Sukumar; Trivedi, Gaurav

doi:10.1109/vlsid.2015.65

Cited by 6 publications

(6 citation statements)

References 15 publications

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“…Truncated multiplication in a MAC architecture has also been studied [32], [33], where the primary aim is to restrict the bit-width of multipliers and produce low error MAC computations by diminishing the effects of truncation. Other design approaches for approximate MAC utilize hybrid redundant adders [34], and an offset compensation to allevi- Approximate MAC designs, (a) utilizing the state-of-the-art self-healing methodology [14], (b) utilizing the proposed ISH methodology (MACISH), where approximation is achieved with ±δ errors within a single multiplier module, which can be averaged out at the accumulator.…”

Section: Background and Related Workmentioning

confidence: 99%

MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing

et al. 2019

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Approximate computing studies the quality-efficiency trade-off to attain a best-efficiency (e.g., area, latency, and power) design for a given quality constraint and vice versa. Recently, self-healing methodologies for approximate computing have emerged that showed an effective quality-efficiency tradeoff as compared to the conventional error-restricted approximate computing methodologies. However, the state-of-the-art self-healing methodologies are constrained to highly parallel implementations with similar modules (or parts of a datapath) in multiples of two and for square-accumulate functions through the pairing of mirror versions to achieve error cancellation. In this paper, we propose a novel methodology for an internal-self-healing (ISH) that allows exploiting self-healing within a computing element internally without requiring a paired, parallel module, which extends the applicability to irregular/asymmetric datapaths while relieving the restriction of multiples of two for modules in a given datapath, as well as going beyond square functions. We employ our ISH methodology to design an approximate multiply-accumulate (xMAC), wherein the multiplier is regarded as an approximation stage and the accumulator as a healing stage. We propose to approximate a recursive multiplier in such a way that a near-to-zero average error is achieved for a given input distribution to cancel out the error at an accurate accumulation stage. To increase the efficacy of such a multiplier, we propose a novel 2 × 2 approximate multiplier design that alleviates the overflow problem within an n × n approximate recursive multiplier. The proposed ISH methodology shows a more effective quality-efficiency trade-off for an xMAC as compared with the conventional error-restricted methodologies for random inputs and for radio-astronomy calibration processing (up to 55% better quality output for equivalent-efficiency designs).

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Section: Background and Related Workmentioning

confidence: 99%

MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing

et al. 2019

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“…Existing work on approximate MAC unit is very scarce comapred to other functional units. For example, Dutt et al [12] proposed an approximate radix-2 hybrid redundant MAC unit based on a redundant number system. The proposed design exploits an approximate hybrid redundant adder as the basic building block for both addition and multiplication operations in the MAC unit.…”

Section: Related Workmentioning

confidence: 99%

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

2019

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The Multiply-Accumulate Unit (MAC) is an integral computational component of all digital signal processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered ''Internet of Things'' (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. Approximate computing (AxC) has been proposed as a potential solution for this problem targeting error-resilient applications. In this paper, we present a novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by: performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation. We propose an input-aware conditional block to bypass operands multiplication by (1) zero forwarding for zero-value operands, (2) judiciously approximating 43.8% of inputs into power-of-2 values, and (3) replacing the multiplication of power-of-2 operands by a simple shift operation. Experimental results show that these simplification techniques reduce delay, power and energy consumption with an acceptable quality degradation. We evaluate the effectiveness of the proposed AxMAC units on two image processing applications, i.e., image blending and filtering, and a logistic regression classification application. These applications demonstrate a negligible quality loss, with 66.6% energy reduction and 5% area overhead. INDEX TERMS Approximate computing, approximate multiplier, approximate multiple-accumulate unit (AxMAC), input-aware approximation, image processing, FPGA.

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“…Furthermore, the use of redundant binary adders (RBAs) makes a more regular interconnection network and modular partial product summing tree structure. Recently, an RB multiply-and-accumulate (MAC) unit has also shown to exhibit high-performance and energy efficiency for error-resilient applications due to its elimination of carry propagation chain [20]. Advocators are optimistic that the inherent carry-free addition and structural regularity of RB multiplier architecture offer significant room for both power and latency reduction.…”

Section: Introductionmentioning

confidence: 99%

Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Yang

Chang

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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The state-of-the-art digital signal processing applications play an important role in making the complex real-time algorithms for speech, audio, image processing, video, control and communication systems economically feasible [1][2][3][4]. Multiplication is one of the most commonly used arithmetic operators in these applicationspecific datapaths. Comparing with many other arithmetic operations, multiplication is time consuming and power hungry. The critical paths dominated by digital multipliers often impose speed limits on the entire design. Therefore, there have been an immense volume of publications and endless research interest in the design of energy efficient digital multipliers at different design abstraction levels [5][6][7][8].Most digital multiplier designs are based on the two's complement arithmetic, which is referred to as normal binary (NB) arithmetic as opposed to the redundant binary (RB) arithmetic studied in this chapter. Fast NB multipliers use modified Booth encoders, and 3-to-2 counters or 4-to-2 compressors in a tree structure for parallel computation [9][10][11]. In the last three decades, most speed improvements in this architecture have been achieved via extreme circuit optimization and the use of advanced fabrication technology. The gain resulting from architectural innovation is almost stagnant. It is conjecture that new insight into energy efficient multiplier design is likely to be derived from an alternative arithmetic with a different Y. He ( ) •

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A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications

Cited by 6 publications

References 15 publications

MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing

MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

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