A comparative survey of approximate adders

Dutt, Sunil; Nandi, Sukumar; Trivedi, Gaurav

doi:10.1109/radioelek.2016.7477392

Cited by 20 publications

(7 citation statements)

References 13 publications

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“…S is the sum output. Adapted from [81]. all sub adders' input carry is set to zero, and all sub adders work in parallel.…”

Section: B Hardware Levelmentioning

confidence: 99%

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate

Endoh

2020

IEEE Access

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The emerging of deep neural networks, especially the convolutional neural network (CNN), substantially promotes the fast development of brainware processors in object detection. However, the vast network architecture brings severe challenges to the design of brainware processor, which requires a large number of logic gates and memories. Therefore, a compact brainware processor with less memory and logic gate has a high demand in object detection. Typically, the object detection involves single-shot and multishot detectors in accordance with different detection principle. In the early stage, the multi-shot detector has a leading role in solving object detection issues, such as region-based convolutional neural networks (R-CNNs), faster R-CNNs etc. However, the multi-shot detector suffers from a low detection rate comparing with the single-shot detector. The you only look once (YOLO) algorithm, as the state-of-the-art real-time object detection algorithm, receives extensive attention from the academics and industry. Particularly, the lightweight YOLO algorithm, tiny YOLO3, has excellent potential for circuit design of compact brainware processor. Nonetheless, systematic studies of tiny YOLO3 are still missing up to the present. This paper offers a thorough review of the tiny YOLO3 algorithm, which can fill the gap in the field of object detection. Furthermore, the open solutions of compressing the tiny YOLO3 algorithm are proposed from the aspects of algorithm, hardware and emerging technology. The comprehensive study presented in this paper can not only enhance understanding of the tiny YOLO3 algorithm for researchers or engineers but also make a significant contribution to accelerating the development of compact brainware processor. INDEX TERMSTiny YOLO3, brainware processor, deep neural network, CNN, hardware acceleration VOLUME 4, 2016 II. RELATED WORK A. YOLO DEVELOPMENT J. Redmon firstly proposed the YOLO algorithm in May 2016 [22], and it has been evolved to four generations within four years. The base YOLO, motivated by fast R-CNNs, introduces the region-based concept to the neural network.Peculiarly, the input image is divided into different grid cells where two bounding boxes are predicted. In each bounding box, the center coordinate of object, confidence scores and the class probabilities are predicted. The confidence score is responsible for checking whether or not the object exists in the bounding box. The base YOLO has a good advantage in the perspective of speed and acceptable accuracy, but the following drawbacks retard the development of base YOLO:• The base YOLO is hard to handle the situation that the distance of two objects is very close. The detector may

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“…S is the sum output. Adapted from [81]. all sub adders' input carry is set to zero, and all sub adders work in parallel.…”

Section: B Hardware Levelmentioning

confidence: 99%

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate

Endoh

2020

IEEE Access

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“…A survey of approximate adders are presented in previous studies. [6][7][8][9] Approximate mirror adders (AMAs) 10 are realized with lesser number of transistors. This results in reduction of circuit complexity, node capacitance, and dynamic power dissipation.…”

Section: Introductionmentioning

confidence: 99%

“…The key feature in designing a approximate full adder (AFA) is to reduce the carry propagation time and hardware reduction. A survey of approximate adders are presented in previous studies . Approximate mirror adders (AMAs) are realized with lesser number of transistors.…”

Section: Introductionmentioning

confidence: 99%

Low power and area efficient error tolerant adder for image processing application

Priyadharshni

Sundaram

2020

Circuit Theory & Apps

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Approximate computing-based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1-bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16-bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05×10 −5 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal-to-noise ratio (PSNR). KEYWORDSapproximate carry select adder, approximate computing, approximate full adder, imprecise full adder, error tolerant adder Int J Circ Theor Appl. 2020;48:696-708. wileyonlinelibrary.com/journal/cta

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“…Over the past decade, several research works have been proposed in the approximate computing paradigm at both software level and hardware level of abstraction [5, 6]. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant interest for approximation [7, 8]. The key design approach behind all existing approximate adders is to limit the length of carry propagation based on the observation that in most of the cases, the length of carry propagation in an N ‐bit conventional adder is

≃ normallo g_{2} N

[9].…”

Section: Introductionmentioning

confidence: 99%

“…One of the key features ofESA‐based approximate adders is that they provide a high degree of designflexibility and programmability as compared to AFA‐based approximate adders. Acomparative review of these approximate adders can be found in [7, 8].…”

Section: Introductionmentioning

confidence: 99%

Accuracy enhancement of equal segment based approximate adders

Dutt

Nandi

Trivedi

2018

IET Computers & Digital Techniques

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Recently, several approximate adders have been proposed based on the design concept of Equal Segment Adder (ESA), i.e. to segment an N-bit adder into several smaller and independent equal size sub-adders. In this study, the authors propose analytical models to estimate Pass Rate (PR), delay, power and area of ESAs, where PR represents the probability of output to be correct. From the proposed analytical models, they observe that there is a scope and need for improvement in quality-effort curves of existing ESAs. Intended to improve the quality-effort curves, they propose modifications in existing ESAs with design objective that modified ESAs provide higher accuracy without imposing any additional delay, power and area overheads. Both the authors' analytical and simulation results show that modified ESAs provide higher accuracy, better qualityeffort curves and more optimal Delay-Power-Area-Accuracy trade-off as compared to original ESAs. In addition to accuracy enhancement, the proposed approach also provides improvements in delay and power when ESAs are used with Error Detection and Correction logic. For evaluating the effectiveness of the proposed approach in real-life applications, they process Lena image using original ESAs and modified ESAs. Their image processing results show that modified ESAs provide more precise images as compared to original ESAs.

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A comparative survey of approximate adders

Cited by 20 publications

References 13 publications

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate

Low power and area efficient error tolerant adder for image processing application

Accuracy enhancement of equal segment based approximate adders

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