Accuracy enhancement of equal segment based approximate adders

Abstract

Recently, several approximate adders have been proposed based on the design concept of Equal Segment Adder (ESA), i.e. to segment an N-bit adder into several smaller and independent equal size sub-adders. In this study, the authors propose analytical models to estimate Pass Rate (PR), delay, power and area of ESAs, where PR represents the probability of output to be correct. From the proposed analytical models, they observe that there is a scope and need for improvement in quality-effort curves of existing ESAs. Intended to improve the quality-effort curves, they propose modifications in existing ESAs with design objective that modified ESAs provide higher accuracy without imposing any additional delay, power and area overheads. Both the authors' analytical and simulation results show that modified ESAs provide higher accuracy, better qualityeffort curves and more optimal Delay-Power-Area-Accuracy trade-off as compared to original ESAs. In addition to accuracy enhancement, the proposed approach also provides improvements in delay and power when ESAs are used with Error Detection and Correction logic. For evaluating the effectiveness of the proposed approach in real-life applications, they process Lena image using original ESAs and modified ESAs. Their image processing results show that modified ESAs provide more precise images as compared to original ESAs.

Design and analysis of a novel fast adder using logical effort method

“…The speed and accuracy of an operator in a digital system mainly depend on its adders' performance [3]. Therefore, enhancing the performance of digital adders is a crucial necessity to have efficient operators in logical circuits [4].…”