Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency

Garg, Bharat; Patel, Sujit Kumar

doi:10.1007/s11265-020-01542-1

Cited by 9 publications

(6 citation statements)

References 23 publications

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“…The proposed adder, an accurate adder (RCA), and six existing approximate adders (LOA, OLOCA, HOAANED, AMA5, ETAI, and SETA) were designed in Verilog-HDL and synthesized with a 65-CMOS technology using Syn- [10,25,26,27]. Also, the error metrics, such as mean ED (MED) and mean RED (MRED), were extracted under 10 7 random inputs.…”

Section: Resultsmentioning

confidence: 99%

DCPA: approximate adder design exploiting dual carry prediction

Choi

Shim

Seok

et al. 2021

IEICE Electron. Express

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Section: Resultsmentioning

confidence: 99%

DCPA: approximate adder design exploiting dual carry prediction

Choi

Shim

Seok

et al. 2021

IEICE Electron. Express

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“…The above applications require multi-bit adders and producing high delay due to rippling of long carry propagations are the great issue in adders. Hence, there is a need in designing of high speed and low complexity architectures of adder [5].…”

Section: Review Of Additionmentioning

confidence: 99%

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Thamizharasan,

Parthipan

2023

Preprint

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In emerging digital world, the high-performance arithmetic computing module with low power and reduced area are required to compute the Signal processing application operations. In that signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and arithmetic & logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplication and it used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor for application of Cryptography and signal processing system. The proposed hybrid compressor-based multiplier is designed and implemented in FPGA (spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on CLA (28.49%), Vedic Multiplier based on RCA (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on HCA (20.10%) and Hybrid multiplier using CSELA (17.81%) and Hybrid Vedic Multiplier (7.15%).

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“…It is important to note that the adder is designed by structural and gate-level modeling to minimize the impact of the synthesis and optimization on the design. Prior studies suggested that a size of 7 to 9 bits for the inaccurate part would be appropriate to obtain a good tradeoff between output quality and power and energy saving for practical applications, such as video and image processing, and a 16-bit adder was widely adopted in these applications [7], [9], [23], [32], [39]. Therefore, we chose the adder design parameters of n = 16 and k = 8.…”

Section: A Experiments Setup and Evaluationmentioning

confidence: 99%

“…Particularly, we considered Gaussian smoothing filtering, which is achieved by a 2-D convolution of an image and Gaussian kernel and used the peak signal-to-noise ratio (PSNR) to measure the output image quality. The following 5×5 Gaussian kernel G is used for filtering [39].…”

Section: A Digital Image Processingmentioning

confidence: 99%

A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation

et al. 2021

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This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. Particularly, the proposed carry prediction technique can reduce a prediction error rate by up to 75% compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). Our experimental results show that the proposed adder improves the normalized mean ED (NMED) and mean relative ED (MRED) by up to 91.4% and 98.9%, respectively, compared to the other approximate adders. Importantly, an excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Specifically, the proposed adder achieves up to 95.7%, 91.1%, and 93.2% reductions of the power-NMED, energy-NMED, and area-delay product (ADP)-NMED products, respectively, compared to the other adders. Our adder enhances the power-, energy-, and ADP-MRED products by up to 99.4% compared to the others. In particular, the figure of merit (FoM) considering both hardware and accuracy of the proposed adder is up to 99.95% smaller than that of the other approximate adders considered herein. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.

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Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency

Cited by 9 publications

References 23 publications

DCPA: approximate adder design exploiting dual carry prediction

DCPA: approximate adder design exploiting dual carry prediction

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation

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