A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation

Abstract

This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. Particularly, the proposed carry prediction technique can reduce a prediction error rate by up to 75% compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). Our experimental results show that the proposed adder improves the normalized mean ED (NMED) and mean relative ED (MRED) by up to 91.4% and 98.9%, respectively, compared to the other approximate adders. Importantly, an excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Specifically, the proposed adder achieves up to 95.7%, 91.1%, and 93.2% reductions of the power-NMED, energy-NMED, and area-delay product (ADP)-NMED products, respectively, compared to the other adders. Our adder enhances the power-, energy-, and ADP-MRED products by up to 99.4% compared to the others. In particular, the figure of merit (FoM) considering both hardware and accuracy of the proposed adder is up to 99.95% smaller than that of the other approximate adders considered herein. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.

A First Experimental Study of Fixed-Point Approximate Arithmetic in Recursive Lattice Filters

“…Bit indexing from to da −1 which is opposite to the original work having index n − 1 to 0. Based on [15]. length equals d m +1 bit which is a consequence of the potential multiplication with ±2, according to Equ.…”

“…We use a recently published AxC adder denoted the Error Reduced Carry Prediction Approximate Adder (ERC-PAA), [15], shown in Fig. 3.…”

Low Power Adders for Efficient Image Processing Applications

“…In this scheme, full adders primarily use SRAM-based sense amplifiers and it is used to smooth images in image processing applications. J. Lee et al, [7] proposed an approximate adder with truncation methods and decreased error distance with improvised mean values. This scheme is used in applications of machine learning, Digital Image Processing (DIP).…”

Error Reduced Carry Prediction in Approximate Addition for Low-Frequency Sound Zones

“…A predicted carry calculated in the inaccurate part is fed into the accurate part. Courtesy of [11] (note however that we use bit indexing from 0 to d − 1 which is opposite to the original work where the bits are indexed n − 1 down to 0). fixed-point multiplier with a word-length of 8 bits as suggested in [10].…”

“…Basically, we evaluate the possibilities of employing approximate addition as an alternative to exact addition. We apply a recently published approximate adder design denoted Error Reduced Carry Prediction Approximate Adder (ERCPAA), [11]. It has better or similar performance than a variety of other approximate adders in terms of metrics such as i) carry prediction error rate, ii) mean relative error distance, and iii) normalized mean error distance as compared to power, energy and area-delay product.…”