LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing

Garg, Bharat; Patel, Sujit Kumar; Dutt, Sunil

doi:10.1007/s10836-020-05883-4

Cited by 25 publications

(12 citation statements)

References 21 publications

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“…Ref. [12] proposed a novel leading one bit-based approximate (LoBA) multiplier architecture, which selects k bits from n-bit inputs (k ≤ n/4) based on leading one bit (LOB) and then computes the approximate product based on these small inputs. Four 4-2 compressors were proposed in Ref.…”

Section: Related Workmentioning

confidence: 99%

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

et al. 2022

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In the field of integrated circuits, the computational cost has always been a crucial design metric. In recent years, with the continuous development in the field of computing, the requirements for computation have been growing rapidly. Reducing the computational cost and improving computational efficiency have become the key issues in the field. There are many error-tolerant applications in the multimedia field where approximate computing techniques can be applied to improve computational efficiency and reduce computational costs at the cost of acceptable computational errors. This paper proposed a piecewise linear Mitchell algorithm based on Mitchell logarithmic approximation multiplication algorithm. Additionally, the Pwl-Mit multiplier is designed according to the improved algorithm combined with the data truncation technique. The proposed approximate multiplier has better statistical performance compared with the state-of-the-art multipliers. The design is simulated and synthesized at the TSMC 65 nm process, and its reliability is verified using discrete cosine transform (DCT) transform.

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Section: Related Workmentioning

confidence: 99%

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

et al. 2022

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“…However, the accuracy of ASSIM declined with increased input bit width [8]. Bharat Garg et al have deliberated a LOB-based IM (LOBIM), which fostered a nal inaccurate product that speci es j-bit from the kbit input and hangs on LOB-logic [9]. The accuracy and design metrics of this IM depend on the chosen k-bits.…”

Section: State-of-the-art Imsmentioning

confidence: 99%

“…Table 2 bestows the design metrics of state-of-the-art IMs and proposed multipliers in terms of delay, area, energy, and power, from which it is divulged that the proposed 8-bit LBSSIM0 and LBSSIM1 slump the energy consumption compared to DRIM, ASSIM, LOBIM, and RAIM. Moreover, the proposed multipliers plunge the delay and power on an average of 28.32%, 48.23%, and 68.23%, respectively, over past 8-bit IMs [7], [8], [9], [10]. The underneath Table 3 exhibits the design metric analysis of 16-bit proposed and current multipliers, from which it is proclaimed that the suggested multipliers dwindled energy compared to DRIM, ASSIM, LOBIM, and RAIM.…”

Section: Design Metrics Analysismentioning

confidence: 99%

Efficient Design of Static Segment Inaccurate Multiplier using Leading One-Bit Approach for Image Processing Applications

Daram

Srinivasa

2022

Preprint

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Traditionally, Image processing applications perform momentous data refinement. One of the most efficacious methods for data manipulation in multiple image processing applications is approximate computing. This mitigates the circuit complexity and thereby reinforces the power, latency, and area metrics. Furthermore, multiplication is also an essential operation in most image-processing applications. In the current scenario, numerous existing state-of-the-art multipliers employed approximation computation techniques to raise the design metrics with limited accuracy. As a consequence, this paper instigates two novel multipliers, namely, one-bit Based Static Segment Inaccurate Multipliers - LBSSIM0 and LBSSIM1, with and without a Hybrid Estimator Logic Circuit (HELC), so as to revamp the accuracy and design metrics. The HELC function is to efface the lower-order significant input bit width data and conceal the inaccurate multiplication of the proposed LBSSIM designs using the barrel shifter and the leading unit. The preferred inaccurate multipliers are simulated and synthesized using Xilinx Vivado, MATLAB, and Cadence RTL compilers for the input widths of 8-bit, 16-bit, and 32-bit. The results reveal that the recommended LBSSIMs dwindle the delay, area, energy, and power on an average of 32.13%, 65.23%, 57.12%, and 64.3%, respectively, with the state-of-the-art Inaccurate Multipliers (IMs). It is also unveiled through the simulation results that the proposed LBSSIMs reinforce the performance of accuracy metrics, namely, MRED, NED, MED, and WCE, on an average of 42.12%, 17.23%, 46.54%, and 28.24%, respectively, as opposed to the state-of-the-art IMs. Eventually, after incorporating the proposed LBSSIMs in the image processing applications, they purveyed higher Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) when collated with the state-of-the-art IMs.

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“…Approximate multiplication is performed by using add and shift logic, but its accuracy depends on the rounded and truncated values. Bharat Garg et al [3] propose a leading one-bit based approximate multiplier, which produces a final product that selects k-bits from the n-bit input operand (based on leading one-bit logic).…”

Section: Literature Surveymentioning

confidence: 99%

“…For example, the error distance (ED), mean error distance (MED), normalized MED (NMED), mean relative error distance (MRED), mean square error distance (MSED), and worst-case error (WCE) are some of the error metrics that are often used to analyze error efficiency in Approximate Multipliers [6,11,15]. Computer simulations are also used to do the error metrics analysis [3,9,17,18,22]. E. Jagadeeswara Rao et al [7] have done a systematic review of recently developed approximate multipliers (nearly 45 approximate multipliers).…”

Section: Introductionmentioning

confidence: 99%

Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application

Rao

Samundiswary

2021

J Electron Test

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We propose a novel, error-efficient approximate multiplier (EEAM), which is based on a rounding-based approach (RBA). Multiplication is performed using rounding, shift, and add operations. We round the input operands to the nearest power of two using RBA. The modified inputs are processed by an arithmetic block (AB), which consists of addition, subtraction, and shifter blocks. The proposed approximate multiplier has input operands whose widths range from 8-bit to 32-bits. We simulated the proposed multiplier by using Vivado and MATLAB. The proposed multiplier is also synthesized using the Cadence RTL compiler, and compared to prior approximate multiplier proposals, EEAM's delay and energy consumption are about of 22% and 57% better than the best known approximate multipliers. We also show that the proposed approximate multiplier's worst-case error, mean error distance, mean relative error distance, and normalized error distance are about 3%, 44%, 45%, and 13% improvement over existing approximate multipliers. Finally, we used the proposed approximate multiplier in an image smoothing filter., For this application, we observed that our multiplier provides higher PSNR and SSIM than any prior approximate multiplier.

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LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing

Cited by 25 publications

References 21 publications

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

Efficient Design of Static Segment Inaccurate Multiplier using Leading One-Bit Approach for Image Processing Applications

Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application

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