A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

Abstract

In the field of integrated circuits, the computational cost has always been a crucial design metric. In recent years, with the continuous development in the field of computing, the requirements for computation have been growing rapidly. Reducing the computational cost and improving computational efficiency have become the key issues in the field. There are many error-tolerant applications in the multimedia field where approximate computing techniques can be applied to improve computational efficiency and reduce computational costs at the cost of acceptable computational errors. This paper proposed a piecewise linear Mitchell algorithm based on Mitchell logarithmic approximation multiplication algorithm. Additionally, the Pwl-Mit multiplier is designed according to the improved algorithm combined with the data truncation technique. The proposed approximate multiplier has better statistical performance compared with the state-of-the-art multipliers. The design is simulated and synthesized at the TSMC 65 nm process, and its reliability is verified using discrete cosine transform (DCT) transform.

Hardware Implementation of an Approximate Simplified Piecewise Linear Spiking Neuron

“…The adder merge result was then multiplied by the time parameter, and was then merged, to obtain the corresponding V n+1 for the current iteration. In this design, we used a segmented carry prediction adder (SCPA) [11] and a Pwl-Mit multiplier [12], as proposed earlier, to approximate the main calculations in the neuron, so as to further decrease the computation cost of the SPWL model.…”