Analysis and Design of Adders for Approximate Computing

Abstract

The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N -bit approximate adder that hereinafter is referred as “ApproxADD.” An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay ( O (1)). ApproxADD also provides improvement in dynamic power consumption by 46.31% and in area by 28.57% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ( N ). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD υ 1 and ApproxADD. We call these as ApproxADD υ 1 and ApproxADD υ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD υ 2.

Low power and area efficient error tolerant adder for image processing application

“…Existing approximate full adders, A, approximate full adder (AFA), B, modified full adder (MFA),C, multiplexer based on approximate full adders (MBAFA)…”

“…Hence, the computational delay of the AFA adder is more. A modified full adder (MFA) is implemented to eliminate the computational delay of carry generation in AFA. However, the MFA suffers from high error distance compared with its counter parts.…”

Design and Analysis of an Energy-Efficient Accuracy Configurable Adder

“…Comparing (5) with (3), we can see that the carry prediction is a pruning-based approximation to carry calculation. Therefore , can be configured to either accurate mode or approximate mode, that is (6) It should be noted that the carry prediction reuses in an existing full adder instead of introducing an additional dedicated circuit as in [46] or Fig.4. This prediction scheme makes an unpretentious modification to the traditional full adder, as shown in Fig.…”

Accuracy enhancement of equal segment based approximate adders

“…In an FA, to secure independent of , should be either 0, 1 or a Boolean function of primary inputs only. As discussed in our previous paper [27], in such scenario, there can be total 16 approximate functions of , where each approximate function corresponds to an AFA. All these 16 AFAs are tabulated in Table 1 with corresponding correct and incorrect entries.…”

“…In this regard, we first design a two‐input NAND gate according to the method of logical effort (see Fig. 2 b in [27]) using Mentor Graphics Tanner schematic capture . We then extract a netlist from the schematic and simulate the extracted netlist using Synopsys HSPICE circuit simulator with PTM 32 nm model files.…”