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Background: Artificial synaptic behaviors are necessary to investigate and implement since they are considered to be a new computing mechanism for the analysis of complex brain information. However, flexible and transparent artificial synapse devices based on thin-film transistors (TFTs) still need further research. Purpose: To study the application of flexible and transparent thin-film transistors with nanometer thickness on artificial synapses. Materials and Methods: Here, we report the design and fabrication of flexible and transparent artificial synapse devices based on TFTs with polyethylene terephthalate (PET) as the flexible substrate, indium tin oxide (ITO) as the gate and a polyvinyl alcohol (PVA) grid insulating layer as the gate insulation layer at room temperature. Results: The charge and discharge of the carriers in the flexible and transparent thin-film transistors with nanometer thickness can be used for artificial synaptic behavior. Conclusion: In summary, flexible and transparent thin-film transistors with nanometer thickness can be used as pressure and temperature sensors. Besides, inherent charge transfer characteristics of indium gallium zinc oxide semiconductors have been employed to study the biological synapse-like behaviors, including synaptic plasticity, excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and long-term memory (LTM). More precisely, the spike rate plasticity (SRDP), one representative synaptic plasticity, has been demonstrated. Such TFTs are interesting for building future neuromorphic systems and provide a possibility to act as fundamental blocks for neuromorphic system applications.

Background: As a key component in artificial intelligence computing, a transistor design is updated here as a potential alternative candidate for artificial synaptic behavior implementation. However, further updates are needed to better control artificial synaptic behavior. Here, an updated channel-electrode transistor design is proposed as an artificial synapse device; this structure is different from previously published designs by other groups. Methods: A semiconductor characterization system was used in order to simulate the artificial synaptic behavior and a scanning electron microscope was used to characterize the device structure. Results: It was found that the electrode added to the transistor channel had a strong impact on the representative transmission behavior of such artificial synaptic devices, such as excitatory postsynaptic current (EPSC) and the paired-pulse facilitation (PPF) index. Conclusion: These behaviors were tuned effectively and the impact of the channel electrode is explained by the combined effects of the joint channel electrode and conventional gate. The voltage dependence of such oxide devices suggests more capability to emulate various synaptic behaviors for numerous medical and non-medical applications. This is extremely helpful for future neuromorphic computational system implementation.

Logic functions are the key backbone in electronic circuits for computing applications. Complementary metal‐oxide‐semiconductor (CMOS) logic gates, with both n‐type and p‐type channel transistors, have been to date the dominant building blocks of logic circuitry as they carry obvious advantages over other technologies. Important physical limits are however starting to arise, as the transistor‐processing technology has begun to meet scaling‐down difficulties. To address this issue, there is the crucial need for a next‐generation electronics era based on new concepts and designs. In this respect, a single‐type channel multigate MOS transistor (SMG‐MOS) is introduced holding the two important aspects of processing adaptability and low static dissipation of CMOS. Furthermore, the SMG‐MOS approach strongly reduces the footprint down to 40% or even less area needed for current CMOS logic function in the same processing technology node. Logic NAND, NOT, AND, NOR, and OR gates, which typically require a large number of CMOS transistors, can be realized by a single SMG‐MOS transistor. Two functional examples of SMG‐MOS are reported here with their analysis based both on simulations and experiments. The results strongly suggest that SMG‐MOS can represent a facile approach to scale down complex integrated circuits, enabling design flexibility and production rates ramp‐up.

Background: Electronic devices which mimic the functionality of biological synapses are a large step to replicate the human brain for neuromorphic computing and for numerous medical research investigations. One of the representative synaptic behaviors is paired-pulse facilitation (PPF). It has been widely investigated because it is regarded to be related to biological memory. However, plasticity behavior is only part of the human brain memory behavior.Methods: Here, we present a phenomenon which is opposite to PPF, i.e., paired-pulse inhibition (PPI), in nano oxide devices for the first time. The research here suggests that rather than being enhanced, the phenomena of memory loss would also be possessed by such electronic devices. The device physics mechanism behind memory loss behavior was investigated. This mechanism is sustained by historical memory and degradation manufactured by device trauma to regulate characteristically stimulated origins of artificial transmission behaviors.Results: Under the trauma of a memory device, both the signal amplitude and signal time stimulated by a pulse are lower than the first signal stimulated by a previous pulse in the PPF, representing a new scenario in the struggle for memory. In this way, more typical human brain behaviors could be simulated, including the effect of age on latency and error generation, cerebellar infarct, trauma and memory loss pharmacological actions (such as those caused by hyoscines and nitrazepam). Conclusion: Thus, this study developed a new approach for implementing the manner in which the brain works in semiconductor devices for improving medical research.

Figure 1 Schematic of the IGZO-based artificial bio synapses, i.e., IGZO TFT. (A) The typical structure of synapses, including the synaptic cleft: pre-and postsynaptic neuron parts. (B) An IGZO TFT device bottom gate structure and the proposed measurement of representative synaptic transmission behavior in IGZO TFT. (Voltage is applied to the bottom gate, and the drain current is the bionic neural signal). (C) SEM top image of IGZO TFTs with an IGZO channel between the source and the drain top electrodes (scale bar=300μm). (D) SEM image of IGZO TFTs layers cross section (scale bar = 100 nm).

Amorphous nano oxides (AO) are intriguing advanced materials for a wide variety of nanosystem medical applications including serving as biosensors devices with p-n junctions, nanomaterial-enabled wearable sensors, artificial synaptic devices for AI neurocomputers and medical mimicking research. However, p-type AO with reliable electrical properties are very difficult to obtain according to the literature. Based on the oxide thin film transistor, a phenomenon that could change an n-type material into a p-type semiconductor is proposed and explained here. The typical In-Ga-Zn-O material has been reported to be an n-type semiconductor, which can be changed by physical conditions, such as in processing or bias. In this way, here, we have identified a manner to change nano material electrical properties among n-type and p-type semiconductors very easily for medical application like biosensors in artificial skin.

Photovoltaic devices have attracted much attention for decades because of their environment-friendly properties and renewable energy prospect. Solar cells with improved electrical properties such as augmented FF (fill factor) and J SC (short-circuit current) are investigated for sustainable energy applications. However, most of research studies focus on the change of materials and the addition of layers. Here, a novel cell with a tilted/nonflatted junction structure is proposed. A detailed study of the key electrical properties for the updated structure with the comparison with the conventional cell structure is presented. The nonflat interface between layers of the semiconductor devices could be extended to different layer interfaces besides the p–n junction, such as the interface between the top electrode and its subsequent layers. Such a nonflat design could be extended to other devices such as photoelectric detectors, lithium battery, capacitors, supercapacitors, and transistors. Simulation results show that the improved structure provides a simple alternative way to improve the key electrical properties for solar cells.