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This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gatelevel functio~nal models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. ASAP considers the performailce improvement of VLSI CMOS circuits by optimally sizing the transistors on the first N critical paths. The global picture of the circuit is considered by taking into account the effects that the transi.stor size changes of one path have on the others. The optimization technique in our sizing tool is based on simulated annealing and couples accurate delay modeling with power and area optimization. The combinatorial minimization of the objective function relies on analytical models that can accurately evaluate the delay, the power and the area of a gate. ASAP has been implemented in C on an Apollo 400 workstation with encouraging results.

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An index fund is a mutual fund that aims to imitate some benchmark index. There are several advantages of investing in an index fund, namely, exposure to a diversified portfolio, minimization of company-specific risks, high liquidity, etc. In India, there has been a significant growth in the number of index funds from 2002 onwards. Today there are more than 20 index funds imitating the NIFTY or SENSEX. In this article, we review and compare a number of Indian index funds. The CRISIL composite ranking of an index fund reflects the quarterly performance of that fund and is subject to fluctuations. We are interested in those index funds that do not deviate significantly from the underlying benchmark index in the long run. This ensures that an investor gets the benefit of any strong rally in the benchmark index, which the index fund imitates. We identify some index funds that satisfy our criteria, and are also ranked above three (indicating above average performance) in the CRISIL rankings of March 2011 and December 2010.

This paper develops a methodology for the design of the memory and the memory-processor communication network in video signal processors. The memory subsystem is the bottleneck of most video computing systems and its design requires evaluating tradeoffs between area, cycle time, and utilization. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture, particularly video signal processing (VSP) systems, and present a systematic method whereby the organization of the memory architecture-the granularity of memory partitioning and the size and type of interconnection network-can be analyzed and its cycle-time approximated before a detailed design is undertaken. We show how variations in sizes and circuit configurations help determine the variations in delay of both memory and network, and how the delay curves, thus determined, can be used to design, compare, and choose from different memorysystem architectures; we also describe a technique that can be used to identify the on-chip-off-chip boundary with respect to a hierarchical memory-system design for a memory-intensive VSP module. All of our results are validated via layout and simulation of prototype circuits in two different process technologies. Motion estimation and discrete cosine transform (DCT) being two of the most important tasks in video processing, we use the design of a motion estimator and that of a DCT unit as examples to illustrate the high-level issues in designing the memory architecture for a VSP module. The analysis presented for the motion estimator and the DCT unit can also be applied to other processing blocks belonging to the system. Index Terms-Circuit simulation, hierarchical memory architecture, memory bank conflict, multiport memory, multistage interconnection network.

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