ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Dutta, Santanu; Nag, Sudip; Roy, Kaushik

doi:10.1109/iscas.1994.408755

Cited by 22 publications

(15 citation statements)

References 15 publications

(14 reference statements)

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“…Figure 6-Figure17 shows comparative analysis of the circuits stated above at 90nm, 45nm and 32nm technology. The simulation results reveal that 10T Modified SRAM Cell at 90nm and 45nm technology and 10T SRAM Cell at 32nm technology shows always best performance for the range of power consumption, operating frequency and temperature [3,9]. …”

Section: Simulation Performance and Analysismentioning

confidence: 99%

Performance Evaluation of Different SRAM Cell Structures at Different Technologies

Singh¹

2012

VLSICS

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Section: Simulation Performance and Analysismentioning

confidence: 99%

Performance Evaluation of Different SRAM Cell Structures at Different Technologies

Singh¹

2012

VLSICS

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“…There are numerous potential logic designs that may give good performance as compared to the basic CMOS logic design [3]. The performance estimation of Full Subtractor is predicated on the basis of area, delay and power consumption [4], [12]. To perform the designing, full custom implementation and simulation of Subtractor at the CMOS circuit level suggests CMOS 45nm technology [5].…”

Section: Introductionmentioning

confidence: 99%

Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique

Narwariya¹,

Akashe²

2015

IJCA

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Full Subtractor using Self Controllable Voltage Level (SVL) Technique is designed in this paper. The circuit can supply an increased dc voltage to an active-load circuit required or can decrease the dc voltage supplied to a load circuit under standby mode is developed. Full Subtractor is a consumed low power and low Leakage as compare to conventional design with SVL technique. We may reduce the value of total power dissipation by applying the U-SVL (upper Self Controllable voltage level) technology in which the supply potential is increased and L-SVL (Lower Self Controllable voltage level) technology in which the ground potential is raised. The analysis paper represents how to control power using SVL techniques. The SVL technique based Full Subtractor compared to conventional design that based on power consumption, propagation delay speed and layout area is more preferred. Low-power techniques projected to reduce power in nanoscale CMOS-Very Large Scale Integration (VLSI) systems, Using SVL technique. The result shows that there is significant reduction in Power assimilation of Full Subtractor in reference mode. This design is much useful in designing the system that low power consumed. The circuit is designed using Cadence Tools in 45nm Technology.

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“…Even in current-generation technology, sub threshold leakage power dissipation is comparable to the dynamic power dissipation, and the fraction of the leakage power will increase significantly in the near future. Today"s microprocessor designs devote a large fraction of the chip area [5] to the memory structures. High-performance onchip caches are a crucial component in the memory hierarchy of modern computing systems.In this technique each NMOS and PMOS transistors in the logic gates is split into two transistors as shown in Fig 1 and …”

Section: Introductionmentioning

confidence: 99%

Reduction of Power Dissipation in Logic Circuits

Ijjada¹,

B.Ramparamesh²,

Rao³

2011

IJCA

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The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today"s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. In this paper the main aim is to reduce power dissipation. A new design method for various logical circuits design, which is low power, compared to general Static CMOS logic. In this technique both NMOS transistor and PMOS transistors in various logic circuits is split into two transistors. Leakage current flowing through the NMOS transistor stack reduces due to the increase in the source to substrate voltage in the top NMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor Leakage current flowing through the PMOS transistor stack reduces due to the increase in the source to substrate voltage in the top PMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor. The tool used is TANNER EDA for schematic simulation. The simulation technology used is MOSIS 180nm.

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ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Cited by 22 publications

References 15 publications

Performance Evaluation of Different SRAM Cell Structures at Different Technologies

Performance Evaluation of Different SRAM Cell Structures at Different Technologies

Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique

Reduction of Power Dissipation in Logic Circuits

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