Viper: A multiprocessor SOC for advanced set-top box and digital TV systems

Dutta, Santanu; Jensen, René; Rieckmann, A.

doi:10.1109/54.953269

Cited by 169 publications

(92 citation statements)

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“…Hot-modules are common in real-life SoCs, as some modules are bandwidth limited and in high demand by other units. Hot-modules may be external (e.g., DRAM [8]- [10]) or internal components (caches, CAMs, specialized arithmetic units, special purpose processors, SRAMs [9]). The identities of the hot-modules are usually known in advance as the critical resources affecting system performance.…”

Section: Introductionmentioning

confidence: 99%

Access Regulation to Hot-Modules in Wormhole NoCs

Walter

Cidon

Ginosar

et al. 2007

First International Symposium on Networks-on-Chip (NOCS'07)

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Network on Chip (NoC) may be the primary interconnect mechanism for future Systems-on-Chip (SoC). Real-life SoCs typically include hot-modules such as DRAM controller or floating point unit, which are bandwidth limited and in high demand by other units. In this paper we demonstrate that the mere existence of one or more hot-modules in a wormholebased NoC dramatically reduces network efficiency and causes an unfair allocation of system resources. We demonstrate that a single hot-module destroys the performance of the entire SoC, even if network resources are over-provisioned. In order to resolve the hot-module effect, we introduce a novel low-cost credit based distributed access regulation technique that fairly allocates access rights to the hot-module. Unlike other methods, this technique directly addresses the root cause of network buffer congestion phenomena. Using simulation, we show the effectiveness of the suggested mechanism in various NoC scenarios.

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Section: Introductionmentioning

confidence: 99%

Access Regulation to Hot-Modules in Wormhole NoCs

Walter

Cidon

Ginosar

et al. 2007

First International Symposium on Networks-on-Chip (NOCS'07)

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“…A 'parent' core may contain several 'child' cores, which in turn may contain their own embedded ('grandchild') cores. For example, [3,4] describe SOCs for digital video, where the SOC design is partitioned into chiplets, which in turn consist of embedded cores. Despite this, most prior research on SOC testing (unrealistically) assumed that there is no design and test hierarchy, i.e., that all cores are at the same hierarchy level [6,7,2].…”

Section: Introductionmentioning

confidence: 99%

Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

Sehgal

Goel

Marinissen

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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“…The designs P1-P3 are simplified versions of set-top box SoCs [9] and the design P4 is a video processing SoC used in TVs. Each use-case has a large number of (50 to 150) communicating pairs of components.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…As an example, a SoC for a set-top box has multiple resolution video processing capabilities (like high definition, standard definition), multiple picture modes (like split-screen, picture-in-picture), video recording features, high speed internet access and file transfer services, etc. [9]. Such convergence of multiple use-cases on to the same device is being observed in other electronic devices as well, such as the cell-phone or the personal digital assistant.…”

Section: Introductionmentioning

confidence: 95%

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Mapping and configuration methods for multi-use-case networks on chips

Murali

Coenen

Radulescu

et al.

Asia and South Pacific Conference on Design Automation, 2006.

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To provide a scalable communication infrastructure for Systems on Chips (SoCs), Networks on Chips (NoCs), a communication centric design paradigm is needed. To be cost effective, SoCs are often programmable and integrate several different applications or use-cases on to the same chip. For the SoC platform to support the different use-cases, the NoC architecture should satisfy the performance constraints of each individual use-case. In this work we motivate the need to consider multiple use-cases during the NoC design process. We present a method to efficiently map the applications on to the NoC architecture, satisfying the design constraints of each individual use-case. We also present novel ways to dynamically reconfigure the network across the different use-cases and explore the possibility of integrating Dynamic Voltage and Frequency Scaling (DVS/DFS) techniques with the use-case centric NoC design methodology. We validate the performance of the design methodology on several SoC applications. The dynamic reconfiguration of the NoC integrated with DVS/DFS schemes results in large power savings for the resulting NoC systems.

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Viper: A multiprocessor SOC for advanced set-top box and digital TV systems

Cited by 169 publications

References 1 publication

Access Regulation to Hot-Modules in Wormhole NoCs

Access Regulation to Hot-Modules in Wormhole NoCs

Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

Mapping and configuration methods for multi-use-case networks on chips

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