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The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test pattems from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test pattems and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.

The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM