Effective and efficient test architecture design for SOCs

A reconfigurable power-conscious core wrapper and its application to soc test scheduling

“…The results are collected in Table 3. In some cases the previously reported results are below the lower bound computed by Goel and Marinissen [6]. These results are Figure 18.…”

“…For illustration, we have made experiments using the P93791 design, one of the largest ITC'02 benchmarks [20]. We have made a test time comparison between our approach and techniques proposed by Goel and Marinissen [6,7,8], Huang et al [9], Iyengar et al [12,13,14], Koranne [15], and Koranne and Iyengar [16]. In our implementation we made use of the wrapper chain algorithm proposed by Iyengar et al [12].…”

“…Several test scheduling techniques have been proposed [1,4,6,7,8,9,11,12,13,14,15,16,17,18]. Chou et al proposed a technique for general systems where each test has a fixed test time and a fixed power consumption value [4].…”

“…And vice versa. Several wrapper chain configuration and TAM wire assignment algorithms to minimize the test time for core tests at wrapped cores have been proposed [6,7,8,9,11,12,13,14,15,16]. For instance, Iyengar et al [12] used an ILP (Integer-Linear Programming) approach.…”

“…• design for low power testing where the system is designed to minimize test power consumption, which allows consequently testing at a higher clock frequency [5,21,22,24], and • test scheduling where the tests are organized in such a way that the test time is minimized while considering test power limitations and test conflicts [1,4,6,7,8,9,11,12,13,14,15,16,17,18].…”