This article deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC with specified parameters of modules and their tests, we design an architecture that minimizes the required tester vector memory depth and test application time. In this article, we formulate the test architecture design problems for both modules with fixed-and flexible-length scan chains, assuming the relevant module parameters and a maximal SOC TAM width are given. Subsequently, we derive a formulation for an architecture-independent lower bound for the SOC test time. We analyze three types of TAM under-utilization that make the theoretical lower bound unachievable in most practical architecture instances. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and TestRail architectures with either serial or parallel test schedules. Experimental results for the ITC'02 SOC Test Benchmarks show that, compared to manual best-effort engineering approaches, we can save up to 75% in test times, while compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
The present paper explores the association between earnings management and specific board characteristics and the firm's profitability in the Indian context. In India, the corporate ownership model is the promoter dominated shareholders model. This is the first study based on a panel data framework that employs a fixed effect model to control for time‐invariant endogeneity. It also contributes to the literature by exploring the role of the firm's profitability in transmitting the impact of audit committee independence on earnings management. The study finds that profitability is an important variable, as it moderates the association between audit committee independence and earnings management. Managers of a profit‐making company would have little need to modify their earnings. This signifies that independent audit committees are more effective monitors of earnings management in profitable firms than in non‐profitable firms. Independent directors with multiple directorships are also found to be ineffective monitors. The findings are of material significance to policymakers in analysing board effectiveness and earnings management and improving policymaking for corporate governance by using profitability and related variables.
PurposeTo review and explore optical fiber and carbon nanotube (CNT) as prospective alternatives to copper in VLSI interconnections.Design/methodology/approachAs the technology moves to deep submicron level, the interconnect width also scales down. Increasing resistivity of copper with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores various alternatives to copper. Metallic CNTs, optical interconnects are promising candidates that can potentially address the challenges faced by copper.FindingsAlthough, the theoretical aspects proves CNTs and optical interconnect to be better alternative against copper on the ground of performance parameters such as power dissipation, switching delay, crosstalk. But copper would last for coming decades on integration basis.Originality/valueThis paper reviews the state‐of‐the‐art in CNT interconnect and optical interconnect research; and discusses both the advantages and challenges of these emerging technologies.
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