Wrapper design for embedded core test

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

“…Figure 7a shows the typical ordering of elements in a wrapper chain for a conventional wrapper, which uses a dedicated TAM. As defined in [21], input wrapper cells are followed by internal scan chains, which are followed by output wrapper cells. Such a wrapper chain receives one stimulus bit every clock cycle; subsequently it takes s in scan cycles to fill the wrapper chain with stimuli.…”

Wrapper design for testing IP cores with multiple clock domains

“…These TAMs are connected to the embedded cores using special interfaces called core wrappers [12]. Recently a number of approaches have addressed core wrapper design (e.g., [6][7][8]10] only to name a few relevant ones). The work in [10] proposes a "test collar" as a test wrapper for SOC test.…”

“…The TestShell is scalable and supports the operating modes required by the IEEE P1500. Wrapper design optimization to reduce testing time was proposed in [8] and [6] introduced an algorithm (based on a best fit decreasing heuristic) to minimize core testing time and required TAM width at the same time.…”

“…The existing wrapper design algorithms developed for IP-protected cores (e.g., [6][7][8]10]) are not directly applicable to at-speed multi-frequency testing because of the clock skew problem during test [5]. Although by grouping the flip-flops triggered by the same clock together and adding lock-up latches in between different clock domains, clock skew problem during shift can be solved (for mux-based scan approach), clock skew during at-speed capture still might occur and corrupt the test response.…”

“…The WSCs are composed from the input/output wrapper cells and the internal scan chains. When using single-frequency core wrappers, the testing time (in seconds) will be a function of the longest WSC [8] and the single shift frequency f , given be the following equation:…”