A reconfigurable power-conscious core wrapper and its application to soc test scheduling

Larsson, Erik; Peng, Zebo

doi:10.1109/test.2003.1271102

Cited by 30 publications

(23 citation statements)

References 25 publications

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“…To be specific, we need: (i) certain multiplexers to select the different test data source for pre-bond test and post-bond test (see the "×" point shown in Fig. 3(b)); (ii) reconfigurable test wrappers for cores that have different TAM width between pre-bond test and post-bond test (e.g., [9,10]); (iii) the necessary control mechanisms (typically by introducing extra instructions in test wrapper and JTAG controller).…”

Section: Motivationmentioning

confidence: 99%

“…Note that, the SA procedure guarantees that we are able to reach all possible core assignment solutions with limited number of movements. Then, for each solution, the heuristic-based TAM width allocation procedure is called (see Fig.11), which starts from the initial solution (line 1) and iteratively tries to find the TAM that leads to the lowest total test cost after assigning one-bit wire (line [5][6][7][8][9][10][11][12]. In line 7, we use proposed greedy reusable heuristic (as shown in Fig.…”

Section: Scheme 2: Tam Wire Reuse With Flexible Pre-bond Test Architementioning

confidence: 99%

See 1 more Smart Citation

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Jiangs

Chakrabarty

et al. 2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Section: Motivationmentioning

confidence: 99%

Section: Scheme 2: Tam Wire Reuse With Flexible Pre-bond Test Architementioning

confidence: 99%

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Jiangs

Chakrabarty

et al. 2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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show abstract

“…In this paper [10], we propose a reconfigurable power conscious core wrapper, which we include in a preemptive test scheduling algorithm. The core wrapper can be used to regulate the test power at core level while the scheduling approach ensures that the system level power limit is not violated.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling

Larsson

Peng

2008

J Electron Test

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The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach.

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“…The advantage is the increased flexibility for the test scheduling. Larsson and Peng proposed the reconfigurable powerconscious core test wrapper to increase the flexibility for power-constrained test scheduling [19].…”

Section: Introductionmentioning

confidence: 99%

An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers

Yoneda

Imanishi

Fujiwara

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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A reconfigurable power-conscious core wrapper and its application to soc test scheduling

Abstract: 1This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip)

Cited by 30 publications

References 25 publications

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling

An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers

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