Testing embedded-core-based system chips

Zorian, Y.; Marinissen, Erik Jan; Dey, Sujit

doi:10.1109/2.769444

Cited by 226 publications

(151 citation statements)

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“…The common design-for-test approach that enables separate testing of embedded modules is to encapsulate the module with a test wrapper [20]. The test wrapper switches between the functional and test connections of the module.…”

Section: Modular Test With Partial Test Wrappermentioning

confidence: 99%

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Dubois

Marinissen

Azimane

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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The fault coverage for bridge defects in the bit-cell matrix of the initial FIFO test has been improved by inclusion of an additional data background and lowvoltage testing. 100% fault coverage is reached for low resistance bridges. The fault coverage for opens has been improved by a new test procedure including waiting periods.98.4% of the hard bridge defects in the asynchronous control slices can be detected with some modifications of the initial test. Nyckelord KeywordsFIFO testing, FIFO, testing, defect-based testing AbstractNXP Semiconductors (formerly Philips Semiconductors) has created a new embedded asynchronous FIFO module. It is a small and fast full-custom design with Design-for-Test (DfT) functionality. The fault detection qualities of a proposed manufacturing test for this FIFO have been analyzed by a defect-based method based on analog simulation. Resistive bridges and opens of different sizes in the bit-cell matrix and in the asynchronous control have been investigated. The fault coverage for bridge defects in the bit-cell matrix of the initial FIFO test has been improved by inclusion of an additional data background and lowvoltage testing. 100% fault coverage is reached for low resistance bridges. The fault coverage for opens has been improved by a new test procedure including waiting periods.98.4% of the hard bridge defects in the asynchronous control slices can be detected with some modifications of the initial test.

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Section: Modular Test With Partial Test Wrappermentioning

confidence: 99%

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Dubois

Marinissen

Azimane

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Modular test techniques can be used for the effective testing of IP cores embedded in an SoC. To apply and observe the test patterns for an SoC, Test Access Mechanism (TAM) and test wrapper have to be provided to establish test paths [1][2][3][4]. Automatic Test Equipment (ATE) is used as the source and sink of test patterns, and either IEEE 1500 or customized interface is adopted as the test wrapper [5].…”

Section: Introductionmentioning

confidence: 99%

Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC

Song¹,

Jung²,

Kim³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

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“…Each core is tested individually using on-chip isolation hardware called a wrapper. Stimuli and responses travel through the chip to and from the embedded core using a Test Access Mechanism (TAM) [29]. Conventionally, dedicated wires are used to implement the TAM.…”

mentioning

confidence: 99%