Test wrapper and test access mechanism co-optimization for system-on-chip

Iyengar, V.; Chakrabarty, Krishnendu; Marinissen, Erik Jan

doi:10.1109/test.2001.966728

Cited by 148 publications

(427 citation statements)

References 16 publications

Supporting

Mentioning

423

Contrasting

Order By: Relevance

“…2b, several TAM widths have the same test time. For a set of TAM widths with the same test time, a pareto-optimal point is the one with lowest TAM [9]. We can notice that the TAM widths having a low value of the WDC, and hence a small number of idle bits, correspond to the pareto-optimal points.…”

Section: Test Quality Metricmentioning

confidence: 96%

“…Iyengar et al [9] proposed a technique to partition the set of scan chain elements (scan chains and wrapper cells) at each core into wrapper scan chains and connect them to TAM wires in such a way that the total test time is minimised. Goel et al [3] showed that ATE memory limitation is a critical problem.…”

Section: Related Workmentioning

confidence: 99%

“…The scanned elements (scan-chains, input cells, output cells and bidirectional cells) at a core have to be configured into a set of wrapper chains, which are to be connected to a corresponding number of TAM wires. The wrapper scan chains, which are to be connected to the TAM wires, w j , should be as balanced as possible, and we make use of the Design_wrapper algorithm proposed by Iyengar et al [9]. For a wrapper chain configuration at a core i where si i is the longest wrapper scan-in chain and so i is the longest wrapper scan-out chain, the test time for core i is given by [9] t i ðw; tvÞ ¼ ð1 þ maxðsi i ðwÞ; so i ðwÞÞÞ Â tv þ minðsi i ðwÞ; so i ðwÞÞ ð8Þ…”

Section: Test Quality Metricmentioning

confidence: 99%

“…We also need a technique to guide the assignment of cores to the TAMs. We make use of the fact that Iyengar et al [9] made use of, which is that balancing the wrapper scan-in chain and wrapper scan-out chain introduces different number of ATE idle bits as the TAM bandwidth varies. We define TWU i (TAM width utilisation) for a core i at a TAM of width w as TWU i ðwÞ ¼ maxðsi i ðwÞ; so i ðwÞÞ Â w ð9Þ…”

Section: Test Quality Metricmentioning

confidence: 99%

See 3 more Smart Citations

Test data truncation for test quality maximisation under ATE memory depth constraint

Larsson

Edbom

2007

IET Comput. Digit. Tech.

View full text Add to dashboard Cite

Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

show abstract

Section: Test Quality Metricmentioning

confidence: 96%

Section: Related Workmentioning

confidence: 99%

Section: Test Quality Metricmentioning

confidence: 99%

Section: Test Quality Metricmentioning

confidence: 99%

See 2 more Smart Citations

Test data truncation for test quality maximisation under ATE memory depth constraint

Larsson

Edbom

2007

IET Comput. Digit. Tech.

View full text Add to dashboard Cite

show abstract

“…Test architecture design and test scheduling techniques have been proposed while minimizing TAT [13,14] which also has been extended for an abort-on-fail environment [15]. These techniques efficiently reduces the TAT and the utilization of the ATE memory.…”

Section: Introductionmentioning

confidence: 99%

Optimized Integration of Test Compression and Sharing for SOC Testing

Larsson

Eles

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

Compression-based SoC Test Infrastructures

Dalmasso

Flottes

Rouzeyre

2009

VLSI-SoC: Advanced Topics on Systems on a Chip

View full text Add to dashboard Cite

Test Data Compression techniques have been developed for reducing requirements in terms of Automatic Test Equipments. In this paper, we explore the benefits of using these techniques in the context of core-based SoCs. Test Data Compression is used to reduce the system test time by increasing the test parallelism of several cores without the expense of additional tester channels. In this paper, we first discuss the constraints on test architectures and on the design flow inferred by the use of compressed test data. We propose a method for seeking an optimal architecture in terms of total test application time. The method is independent of the compression scheme used for reduction of core test data. The gain in terms of test application time for the SoC is over 50% compared to a test scheme without compression.

show abstract

Test wrapper and test access mechanism co-optimization for system-on-chip

Cited by 148 publications

References 16 publications

Test data truncation for test quality maximisation under ATE memory depth constraint

Test data truncation for test quality maximisation under ATE memory depth constraint

Optimized Integration of Test Compression and Sharing for SOC Testing

Compression-based SoC Test Infrastructures

Contact Info

Product

Resources

About