Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

Abstract

Multiple levels of design hierarchy are common in currentgeneration system-on-chip (SOC)

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

“…In addition to on-chip decompressors, application of compression techniques in SoC designs requires specialized instrumentation such as TAMs (to transport test data between the SoC pins and the embedded cores [9], [37]) and test wrappers (to interface the core and the SoC environment [19], [32], [43]). Typically, TAM and wrapper design schemes are tailored towards optimal test application time [10], [20], [47], test interface [8], [39], power dissipation [6], [18], [26], [31], [35], [49], control logic [28], [46], routing and layout, internal cores hierarchy [3], [4], [11], [38], or mixed-signal tests. There is also a growing interest in solutions that address both TAM/wrapper design and test data compression [22], [42].…”

Composite combinatorial scheme of test planning (example for microprocessor systems)

“…System test processes are very complicated and it exists a real need of decreasing the complexity of the testing procedures (e.g., [1], [5], [13], [22]): (a) reducing the initial "space" of system test inputs, (b) integration of close test operations, (c) selection and/or design of the most important/effective test operations, and (d) effective usage of test engineers (testers). Approaches to test strategies for microprocessor systems have been examined as well (e.g., [10], [7], [9], [16], [26], [29]). This paper addresses the usage of multicriteria combinatorial models for designing an efficient test strategy (plan) for a set of microprocessor systems.…”