EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

Abstract

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

A new mechanism for SOC scan test scheduling

“…Janicki also presented novel schemes for flexible EDT (Embedded Deterministic Test) channel bandwidth management in [3] and [4], the utilization of input and output channels can be much improved. Normally, previous studies on test scheduling were only considering a test set indivisible.…”